公开(公告)号：US08698311B2

公开(公告)日：2014-04-15

申请号：US13599838

申请日：2012-08-30

申请人： Tae-Gyu Kang ,  Ho-Tae Jin ,  Tae-ho Moon ,  Il-soo Choi ,  Jong-Eun Lee

发明人： Tae-Gyu Kang ,  Ho-Tae Jin ,  Tae-ho Moon ,  Il-soo Choi ,  Jong-Eun Lee

IPC分类号： H01L23/48

CPC分类号： H01L24/14 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2224/06102 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/14515 ,  H01L2224/16237 ,  H01L2224/17104 ,  H01L2224/17517 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

摘要： A package substrate may include an insulating substrate, a dummy pad, a signal pad and a plug. The dummy pad may be formed on an upper surface of the insulating substrate. The signal pad may be formed on the upper surface of the insulating substrate. The signal pad may have an upper surface protruded from an upper surface of the dummy pad. The plug may be vertically formed in the insulating substrate. The plug may have an upper end exposed through the upper surface of the insulating substrate and connected with the signal pad and the dummy pad, and a lower end exposed through a lower surface of the insulating substrate. Thus, a signal bump may accurately make contact with the protruded upper surface of the signal pad.

摘要翻译： 封装基板可以包括绝缘基板，虚拟焊盘，信号焊盘和插头。 虚拟焊盘可以形成在绝缘基板的上表面上。 信号焊盘可以形成在绝缘基板的上表面上。 信号垫可以具有从虚拟垫的上表面突出的上表面。 插塞可以垂直地形成在绝缘基板中。 插头可以具有通过绝缘基板的上表面暴露的上端，并且与信号焊盘和虚拟焊盘相连，并且通过绝缘基板的下表面露出的下端。 因此，信号凸块可以准确地与信号垫的突出的上表面接触。

公开(公告)号：US20130069229A1

公开(公告)日：2013-03-21

申请号：US13599838

申请日：2012-08-30

申请人： Tae-Gyu KANG ,  Ho-Tae JIN ,  Tae-ho MOON ,  Il-soo CHOI ,  Jong-Eun LEE

发明人： Tae-Gyu KANG ,  Ho-Tae JIN ,  Tae-ho MOON ,  Il-soo CHOI ,  Jong-Eun LEE

IPC分类号： H01L23/485 ,  H01L23/48

CPC分类号： H01L24/14 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2224/06102 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/14515 ,  H01L2224/16237 ,  H01L2224/17104 ,  H01L2224/17517 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

摘要： A package substrate may include an insulating substrate, a dummy pad, a signal pad and a plug. The dummy pad may be formed on an upper surface of the insulating substrate. The signal pad may be formed on the upper surface of the insulating substrate. The signal pad may have an upper surface protruded from an upper surface of the dummy pad. The plug may be vertically formed in the insulating substrate. The plug may have an upper end exposed through the upper surface of the insulating substrate and connected with the signal pad and the dummy pad, and a lower end exposed through a lower surface of the insulating substrate. Thus, a signal bump may accurately make contact with the protruded upper surface of the signal pad.

摘要翻译： 封装基板可以包括绝缘基板，虚拟焊盘，信号焊盘和插头。 虚拟焊盘可以形成在绝缘基板的上表面上。 信号焊盘可以形成在绝缘基板的上表面上。 信号垫可以具有从虚拟垫的上表面突出的上表面。 插塞可以垂直地形成在绝缘基板中。 插头可以具有通过绝缘基板的上表面暴露的上端，并且与信号焊盘和虚拟焊盘相连，并且通过绝缘基板的下表面露出的下端。 因此，信号凸块可以准确地与信号垫的突出的上表面接触。

公开(公告)号：US07502231B2

公开(公告)日：2009-03-10

申请号：US11950971

申请日：2007-12-05

申请人： Yi-Sung Hwang ,  Ho-Tae Jin ,  Hwan-Young Jang

发明人： Yi-Sung Hwang ,  Ho-Tae Jin ,  Hwan-Young Jang

IPC分类号： H05K7/00

CPC分类号： H05K3/0097 ,  H01L23/13 ,  H01L2924/0002 ,  H05K3/0052 ,  H05K2201/09909 ,  H05K2201/2009 ,  H05K2203/0169 ,  H01L2924/00

摘要： Provided is a thin printed circuit board (PCB) for manufacturing a chip scale package (CSP). The thin printed circuit board includes a plurality of unit printed circuit boards, each of which is comprised of a circuit pattern, to which a semiconductor chip is adhered, and a substrate surrounding the circuit pattern. The unit printed boards are arranged in a row and includes a support molding, which is spaced a predetermined interval apart from the circuit pattern of each unit printed circuit board on the substrate of each unit printed circuit board and formed in a ring shape along the edge of the thin printed circuit board.

摘要翻译： 提供了用于制造芯片级封装（CSP）的薄印刷电路板（PCB）。 薄印刷电路板包括多个单元印刷电路板，每个单元印刷电路板包括电路图案，半导体芯片被粘附到该电路图案和围绕电路图案的基板。 单元印刷电路板排列成一行，并且包括支撑模制件，该支撑模制件与每个单元印刷电路板的基板上的每个单元印刷电路板的电路图案间隔开预定间隔，并且沿着边缘形成为环形 的薄印刷电路板。

公开(公告)号：US07323642B2

公开(公告)日：2008-01-29

申请号：US10893615

申请日：2004-07-16

申请人： Yi-Sung Hwang ,  Ho-Tae Jin ,  Hwan-young Jang

发明人： Yi-Sung Hwang ,  Ho-Tae Jin ,  Hwan-young Jang

IPC分类号： H05K1/03

CPC分类号： H05K3/0097 ,  H01L23/13 ,  H01L2924/0002 ,  H05K3/0052 ,  H05K2201/09909 ,  H05K2201/2009 ,  H05K2203/0169 ,  H01L2924/00

摘要： Provided is a thin printed circuit board (PCB) for manufacturing a chip scale package (CSP). The thin printed circuit board includes a plurality of unit printed circuit boards, each of which is comprised of a circuit pattern, to which a semiconductor chip is adhered, and a substrate surrounding the circuit pattern. The unit printed boards are arranged in a row and includes a support molding, which is spaced a predetermined interval apart from the circuit pattern of each unit printed circuit board on the substrate of each unit printed circuit board and formed in a ring shape along the edge of the thin printed circuit board.

摘要翻译： 提供了用于制造芯片级封装（CSP）的薄印刷电路板（PCB）。 薄印刷电路板包括多个单元印刷电路板，每个单元印刷电路板包括电路图案，半导体芯片被粘附到该电路图案和围绕电路图案的基板。 单元印刷电路板排列成一行，并且包括支撑模制件，该支撑模制件与每个单元印刷电路板的基板上的每个单元印刷电路板的电路图案间隔开预定间隔，并且沿着边缘形成为环形 的薄印刷电路板。

公开(公告)号：US06787393B2

公开(公告)日：2004-09-07

申请号：US10370624

申请日：2003-02-24

申请人： Ho-tae Jin ,  Heui-seog Kim

发明人： Ho-tae Jin ,  Heui-seog Kim

IPC分类号： H01L2144

CPC分类号： H01L24/49 ,  H01L23/3121 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/4918 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package including a double-faced semiconductor chip having integrated circuitry on both sides thereof, and a method of fabricating the same is provided, wherein the semiconductor package includes the semiconductor chip; a lead-on-chip (LOC)-type substrate, having metal patterns on both sides, bonded with the first side of the semiconductor chip; first wires for connecting the first side of the semiconductor chip to the second side of the LOC-type substrate; second wires for connecting the second side of the semiconductor chip to the first side of the LOC-type substrate; a first sealing material for covering the semiconductor chip, the first wires, and the second side of the LOC-type substrate; a second sealing material for covering the semiconductor chip, the second wires, and the first side of the LOC-type substrate; and solder balls attached to the second side of the LOC-type substrate.

公开(公告)号：US06386432B1

公开(公告)日：2002-05-14

申请号：US09710517

申请日：2000-11-10

申请人： Ho Tae Jin ,  Hee Kook Choi

发明人： Ho Tae Jin ,  Hee Kook Choi

IPC分类号： B23K3102

CPC分类号： H01L21/67144 ,  H01L21/6838 ,  H01L2924/0002 ,  H05K13/0409 ,  Y10T29/53191 ,  H01L2924/00

摘要： An embodiment of the present invention provides a pickup tool in accordance with the present invention includes multiple contact parts, which contact a passivation layer of a semiconductor chip so that the contact parts are far from chip pads and fuses when holding the semiconductor chip. Furthermore, a die bonding apparatus has one or two pickup tools, an aligning stage, and a bond stage or a bond head.

摘要翻译： 本发明的一个实施例提供一种根据本发明的拾取工具，其包括多个接触部分，其接触半导体芯片的钝化层，使得当保持半导体芯片时接触部分远离芯片焊盘和熔丝。 此外，管芯接合装置具有一个或两个拾取工具，对准阶段和结合阶段或结合头。

公开(公告)号：US08466074B2

公开(公告)日：2013-06-18

申请号：US13083043

申请日：2011-04-08

申请人： Sung-il Cho ,  Ho-tae Jin ,  Heui-seog Kim ,  Seon-ju Oh

发明人： Sung-il Cho ,  Ho-tae Jin ,  Heui-seog Kim ,  Seon-ju Oh

IPC分类号： H01L21/268

CPC分类号： H01L21/268 ,  H01L21/2007

摘要： A method for processing a substrate includes generating a first laser beam, splitting the first laser beam into a plurality of second laser beams, focusing the split second laser beams on a plane in the substrate parallel to a main surface of the substrate, and performing surface separation of the substrate along the plane.

摘要翻译： 一种用于处理衬底的方法包括：生成第一激光束，将第一激光束分成多个第二激光束，将分裂的第二激光束聚焦在平行于衬底的主表面的衬底的平面上，并且执行表面 沿着平面分离衬底。

公开(公告)号：US20130093080A1

公开(公告)日：2013-04-18

申请号：US13618357

申请日：2012-09-14

申请人： Won-Gil HAN ,  Se-Yeoul Park ,  Ho-Tae Jin ,  Byong-Joo Kim ,  Yong-Je Lee ,  Han-Ki Park

发明人： Won-Gil HAN ,  Se-Yeoul Park ,  Ho-Tae Jin ,  Byong-Joo Kim ,  Yong-Je Lee ,  Han-Ki Park

IPC分类号： H01L21/66 ,  H01L25/00

CPC分类号： H01L24/85 ,  H01L22/14 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/4847 ,  H01L2224/48992 ,  H01L2224/4941 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/8503 ,  H01L2224/85951 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/35 ,  H01L2924/00012 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A multi-chip package may include a first semiconductor chip, a second semiconductor chip, a first stud bump, a first nail head bonding bump, a second stud bump, and a first conductive wire. The first semiconductor chip may have a first bonding pad. The second semiconductor chip may be stacked on the first semiconductor chip so the first bonding pad remains exposed. The second semiconductor chip may have a second bonding pad. The first stud bump may be formed on the first bonding pad. The first nail head bonding bump may be formed on the first stud bump, with one end of a first conductive wire formed between the two. The second stud bump may be formed on the second bonding pad, with another end of the first conductive wire formed between the two. An electrical connection test may be performed on each of the wire bonding processes.

公开(公告)号：US20110256736A1

公开(公告)日：2011-10-20

申请号：US13083043

申请日：2011-04-08

申请人： Sung-il Cho ,  Ho-tae Jin ,  Heui-seog Kim ,  Seon-ju Oh

发明人： Sung-il Cho ,  Ho-tae Jin ,  Heui-seog Kim ,  Seon-ju Oh

IPC分类号： H01L21/268

CPC分类号： H01L21/268 ,  H01L21/2007

摘要： A method for processing a substrate includes generating a first laser beam, splitting the first laser beam into a plurality of second laser beams, focusing the split second laser beams on a plane in the substrate parallel to a main surface of the substrate, and performing surface separation of the substrate along the plane.

摘要翻译： 一种用于处理衬底的方法包括：生成第一激光束，将第一激光束分成多个第二激光束，将分裂的第二激光束聚焦在平行于衬底的主表面的衬底的平面上，并且执行表面 沿着平面分离衬底。

公开(公告)号：US20090028671A1

公开(公告)日：2009-01-29

申请号：US11943046

申请日：2007-11-20

申请人： Ho-Tae Jin ,  Young-Seok Jung ,  Bong-Su Cho

发明人： Ho-Tae Jin ,  Young-Seok Jung ,  Bong-Su Cho

IPC分类号： H01L21/677 ,  H01L21/67

CPC分类号： H01L21/67132 ,  H01L21/67069 ,  H01L21/67173 ,  H01L21/67207 ,  H01L21/67213 ,  H01L21/6723

摘要： An in-line system for manufacturing a semiconductor package according to principles of the present invention can prevent wafer warpage due to a back-lap process and die defects due to sticking of the die. In one embodiment, the in-line system adheres a semiconductor chip to a substrate by coating a liquid adhesive agent on a rear surface of the wafer. The processes of the in-line system are preferably performed in series. More particularly, the in-line system for manufacturing a semiconductor package can include a loading unit for loading a wafer into the system. A back-lap unit can include a grinder configured to back-grind a rear surface of the wafer received from the loading unit. A cleansing unit preferably comprises an air pressure plasma generating unit for cleansing the wafer using air pressure plasma. A coating unit can be configured to form an adhesive layer on a rear surface of the cleansed wafer by using a nozzle to coat a liquid adhesive agent onto the wafer. In the coating unit, the wafer can be rotated or not rotated depending on the desired characteristics of the adhesive layer. An attaching unit is preferably provided to attach a dicing tape on the adhesive layer formed. And an unloading unit unloads the wafer from the system. A transporting unit can be configured to transport the wafer sequentially between the loading unit, the back-lap unit, the cleansing unit, the coating unit, the attaching unit, and the unloading unit. One or more wafer chucks can be mounted to the wafer as the wafer is transported through the manufacturing processes.

摘要翻译： 根据本发明的原理的用于制造半导体封装的在线系统可以防止由于模头的贴合而产生的由于搭接过程而造成的晶片翘曲和模具缺陷。 在一个实施例中，在线系统通过在晶片的后表面上涂覆液体粘合剂将半导体芯片粘附到基底上。 在线系统的处理优选串联进行。 更具体地，用于制造半导体封装的在线系统可以包括用于将晶片加载到系统中的加载单元。 背部搭载单元可以包括配置成后研磨从装载单元接收的晶片的后表面的研磨机。 清洁单元优选地包括用于使用空气压力等离子体清洁晶片的空气压力等离子体产生单元。 涂覆单元可以被配置为通过使用喷嘴将液体粘合剂涂覆到晶片上而在清洁的晶片的后表面上形成粘合剂层。 在涂布单元中，晶片可以根据粘合剂层的期望特性而旋转或不旋转。 优选地设置附接单元以将切割带附接到形成的粘合剂层上。 并且卸载单元从系统卸载晶片。 传送单元可以被配置为在加载单元，后座单元，清洁单元，涂布单元，附接单元和卸载单元之间顺序地传送晶片。 当晶片通过制造工艺传送时，可以将一个或多个晶片卡盘安装到晶片。