利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

45 条记录 (耗时 0.022 秒)

    SEMICONDUCTOR MEMORY DEVICE
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开
    半导体存储器件

    公开(公告)号：US20130088912A1

    公开(公告)日：2013-04-11

    申请号：US13535583

    申请日：2012-06-28

    申请人： Jong-pil SON ,  Dong-min KIM

    发明人： Jong-pil SON ,  Dong-min KIM

    IPC分类号： G11C7/06 ,  G11C11/24 ,  G11C7/00

    CPC分类号： G11C7/08 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4099

    摘要： A semiconductor memory device includes a first bit line to which a first memory cell is connected, and a second bit line to which a second memory cell is connected, the second bit line being complementary to the first bit line, a sense amplifier that includes a first transistor and a second transistor connected in series between the first bit line and the second bit line, the sense amplifier including a first node between the first transistor and the second transistor, a gate of the first transistor being connected to the second bit line, and a gate of the second transistor being connected to the first bit line, and a voltage providing unit that provides a first voltage to the first node during presensing, and provides a second voltage, different from the first voltage, to the first node during main sensing.

    摘要翻译： 半导体存储器件包括第一存储器单元连接到的第一位线和连接第二存储器单元的第二位线，第二位线与第一位线互补，读出放大器包括： 第一晶体管和第二晶体管串联连接在第一位线和第二位线之间，读出放大器包括第一晶体管和第二晶体管之间的第一节点，第一晶体管的栅极连接到第二位线， 并且所述第二晶体管的栅极连接到所述第一位线，以及电压提供单元，其在预定期间向所述第一节点提供第一电压，并且在所述第一节点期间在所述第一节点期间向所述第一节点提供与所述第一电压不同的第二电压 感应。

    SEMICONDUCTOR MEMORY DEVICE INCLUDING SPARE ANTIFUSE ARRAY AND ANTIFUSE REPAIR METHOD OF THE SEMICONDUCTOR MEMORY DEVICE
    5.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE INCLUDING SPARE ANTIFUSE ARRAY AND ANTIFUSE REPAIR METHOD OF THE SEMICONDUCTOR MEMORY DEVICE 审中-公开
    半导体存储器件，包括备用抗体阵列和半导体存储器件的抗体修复方法

    公开(公告)号：US20130003477A1

    公开(公告)日：2013-01-03

    申请号：US13534161

    申请日：2012-06-27

    申请人： Ju-Seop PARK ,  Sin Ho KIM ,  Byung-Sik MOON ,  Jong-Pil SON ,  Jin-Ho KIM ,  Hyoung-Joo KIM ,  Jong-Min OH ,  Seong-Jin JANG

    发明人： Ju-Seop PARK ,  Sin Ho KIM ,  Byung-Sik MOON ,  Jong-Pil SON ,  Jin-Ho KIM ,  Hyoung-Joo KIM ,  Jong-Min OH ,  Seong-Jin JANG

    IPC分类号： G11C11/21 ,  G11C29/44

    CPC分类号： G11C29/027 ,  G11C29/789 ,  G11C29/808

    摘要： A semiconductor memory device including an antifuse cell array and a spare antifuse cell array are provided. An antifuse cell array includes a first set of antifuse cells arranged in a first direction and each one of the first set of antifuse cells is connected to a corresponding one of first through nth word lines. The spare antifuse cell array includes a first spare set of antifuse cells arranged in the first direction and each one of the first spare set of antifuse cells is connected to a corresponding one of first through kth spare word lines. A first operation control circuit is configured to program antifuses of the antifuse cell array and the spare antifuse cell array, and to read a status of each of the antifuses. The first operation control circuit is commonly connected to the first set of antifuse cells and the first spare set of antifuse cells.

    摘要翻译： 提供了包括反熔丝电池阵列和备用反熔丝电池阵列的半导体存储器件。 反熔丝电池阵列包括以第一方向布置的第一组反熔丝元件，并且第一组反熔丝电池中的每一个连接到第一至第n个字线中的对应的一个。 备用反熔断电池阵列包括沿第一方向布置的第一备用组反熔丝单元，并且第一备用组反熔丝单元中的每一个连接到第一至第九备用字线中相应的一个。 第一操作控制电路被配置为编制反冒点电池阵列和备用反熔丝电池阵列的反熔丝，并且读取每个反熔丝的状态。 第一操作控制电路通常连接到第一组反熔丝电池和第一备用反熔丝电池组。

    Semiconductor memory device
    6.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US20060157737A1

    公开(公告)日：2006-07-20

    申请号：US11326159

    申请日：2006-01-05

    申请人： Bo-Tak Lim ,  Su-Yeon Kim ,  Jong-Pil Son ,  Gong-Heum Han

    发明人： Bo-Tak Lim ,  Su-Yeon Kim ,  Jong-Pil Son ,  Gong-Heum Han

    IPC分类号： H01L27/10

    CPC分类号： H01L27/0207 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11898

    摘要： A semiconductor memory device comprises a cell region including a plurality of unit memory cells, and a peripheral circuit region, the peripheral circuit region including a plurality of peripheral circuit devices for operating the plurality of memory cells and at least one operating capacitor formed adjacent to at least one peripheral circuit device at a pseudo circuit pattern region.

    摘要翻译： 一种半导体存储器件包括一个包括多个单元存储单元的单元区域和一个外围电路区域，该外围电路区域包括用于操作该多个存储单元的多个外围电路器件以及邻近形成的至少一个工作电容器 在伪电路图案区域中的至少一个外围电路器件。

    Semiconductor memory device
    7.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US06459642B1

    公开(公告)日：2002-10-01

    申请号：US09703820

    申请日：2000-11-01

    申请人： Beak Hyung Cho ,  Du Eung Kim ,  Jong Pil Son

    发明人： Beak Hyung Cho ,  Du Eung Kim ,  Jong Pil Son

    IPC分类号： G11C700

    CPC分类号： G11C29/83 ,  G11C5/14 ,  G11C29/832

    摘要： The invention discloses a semiconductor memory device in which faulty cells causing standby current failure will be replaced with redundancy cells. The semiconductor memory device includes: a plurality of word lines, a plurality of bit lines, a plurality of cells connected between the word lines and bit lines for storing data and a memory cell array of a plurality of cell blocks having a plurality of cell power lines for providing supply voltage to the cells; a plurality of row decoder circuits for decoding external row addresses and generating selection signals for predetermined word lines included in the cell blocks; and a plurality of cell power repairing circuits for selectively blocking between cell power lines providing supply voltage to faulty cells and power source at an occurrence of faulty cells causing standby current failure. At this time, the cell power lines of the cell blocks are arranged in an identical direction to word lines; the row decoder circuits are respectively arranged between two neighboring cell blocks; and the cell power repairing circuits are respectively arranged between the cell blocks of the memory cell array, thereby reducing the size of a chip.

    摘要翻译： 本发明公开了一种半导体存储器件，其中引起备用电流故障的故障单元将被替换为冗余单元。 半导体存储器件包括：多个字线，多个位线，连接在字线和用于存储数据的位线之间的多个单元，以及具有多个单元电力的多个单元块的存储单元阵列 为电池提供电源电压的线路; 多个行解码器电路，用于解码外部行地址并产生用于包括在单元块中的预定字线的选择信号; 以及多个单元电力修复电路，用于在出现故障单元并导致待机电流故障时，选择性地阻塞在故障单元和电源之间提供电源电压的单元电源线之间。 此时，单元块的单元电力线被排列成与字线相同的方向; 行解码器电路分别布置在两个相邻的单元块之间; 并且电池功率修复电路分别布置在存储单元阵列的单元块之间，从而减小芯片的尺寸。

    MEMORY MODULES AND MEMORY SYSTEMS
    8.
    发明申请
    MEMORY MODULES AND MEMORY SYSTEMS 有权
    存储器模块和存储器系统

    公开(公告)号：US20140189215A1

    公开(公告)日：2014-07-03

    申请号：US14083033

    申请日：2013-11-18

    申请人： UK-SONG KANG ,  Chul-Woo Park ,  Hak-Soo Yu ,  Jong-Pil Son

    发明人： UK-SONG KANG ,  Chul-Woo Park ,  Hak-Soo Yu ,  Jong-Pil Son

    IPC分类号： G11C11/406 ,  G06F12/02

    CPC分类号： G11C11/40607 ,  G11C11/40603 ,  G11C11/40622 ,  G11C11/4087

    摘要： A memory module includes a plurality of memory devices and a buffer chip. The buffer chip manages the memory devices. The buffer chip includes a refresh control circuit that groups a plurality of memory cell rows of the memory devices into a plurality of groups according to a data retention time of tire memory cell rows. The buffer chip selectively refreshes each of the plurality of groups in each of a plurality of refresh time regions that are periodically repeated and applies respective refresh periods to the plurality of groups, respectively.

    摘要翻译： 存储器模块包括多个存储器件和缓冲器芯片。 缓冲芯片管理存储器件。 缓冲芯片包括根据轮胎存储单元行的数据保持时间将存储器件的多个存储单元行分组成多个组的刷新控制电路。 缓冲器芯片有选择地刷新周期性地重复的多个刷新时间区域中的每一个中的多个组中的每一个，并将各个刷新周期分别应用于多个组。

    MEMORY DEVICE FOR REDUCING A WRITE FAIL, A SYSTEM INCLUDING THE SAME, AND A METHOD THEREOF
    9.
    发明申请
    MEMORY DEVICE FOR REDUCING A WRITE FAIL, A SYSTEM INCLUDING THE SAME, AND A METHOD THEREOF 有权
    用于减少写入失败的存储器件，包括其的系统及其方法

    公开(公告)号：US20140068203A1

    公开(公告)日：2014-03-06

    申请号：US14013275

    申请日：2013-08-29

    申请人： JONG PIL SON ,  CHUL WOO PARK ,  HAK SOO YU ,  HONG SUN HWANG

    发明人： JONG PIL SON ,  CHUL WOO PARK ,  HAK SOO YU ,  HONG SUN HWANG

    IPC分类号： G06F3/06

    CPC分类号： G06F3/061 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0676 ,  G06F3/068 ,  G06F13/1642 ,  G11C7/00 ,  G11C7/1048 ,  G11C11/4076 ,  Y02D10/14

    摘要： A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller is configured to continuously perform a plurality of write commands on the memory device between an active command and a precharge command. In the memory system, when after a first write operation having a last write command of the plurality of write commands is performed and then the precharge command is issued, the last write command is issued for a second write operation after the precharge command. The first write operation and the second write operation write a same data to memory cells of plurality of memory cells having a same address.

    摘要翻译： 存储器系统包括存储器件和存储器控制器。 存储装置包括多个存储单元。 存储器控制器被配置为在活动命令和预充电命令之间在存储器设备上连续地执行多个写入命令。 在存储器系统中，当执行了具有多个写入命令的最后写入命令的第一次写入操作之后，然后执行预充电命令时，在预充电命令之后发出最后一个写入命令用于第二次写入操作。 第一写入操作和第二写入操作将相同的数据写入具有相同地址的多个存储单元的存储单元。

    Fuse circuit and semiconductor memory device including the same
    10.
    发明授权
    Fuse circuit and semiconductor memory device including the same 有权
    保险丝电路和包括其的半导体存储器件

    公开(公告)号：US08599635B2

    公开(公告)日：2013-12-03

    申请号：US13205966

    申请日：2011-08-09

    申请人： Jin-Ho Kim ,  Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Seung-Hoon Oh ,  Ju-Seop Park

    发明人： Jin-Ho Kim ,  Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Seung-Hoon Oh ,  Ju-Seop Park

    IPC分类号： G11C17/18

    CPC分类号： G11C29/027 ,  G11C17/16 ,  G11C29/04

    摘要： A fuse circuit includes a program unit, a sensing unit and a control unit. The program unit is programmed in response to a program signal, and outputs a program output signal in response to a sensing enable signal. The sensing unit includes a variable resistor unit that has a resistance that varies based on a control signal, and generates a sensing output signal based on the resistance of the variable resistor unit and the program output signal. The control unit generates the control signal having a value changed depending on operation modes, and performs a verification operation with respect to the program unit based on the sensing output signal to generate a verification result. The program unit may be re-programmed based on the verification result.

    摘要翻译： 熔丝电路包括程序单元，感测单元和控制单元。 程序单元响应于程序信号被编程，并且响应于感测使能信号而输出程序输出信号。 感测单元包括具有基于控制信号而变化的电阻的可变电阻器单元，并且基于可变电阻器单元的电阻和程序输出信号产生感测输出信号。 控制单元产生具有根据操作模式改变的值的控制信号，并且基于感测输出信号执行关于节目单元的验证操作以产生验证结果。 程序单元可以基于验证结果重新编程。