公开(公告)号：US06391752B1

公开(公告)日：2002-05-21

申请号：US09659920

申请日：2000-09-12

申请人： Jean Pierre Colinge ,  Carlos H. Diaz

发明人： Jean Pierre Colinge ,  Carlos H. Diaz

IPC分类号： H01L213205

CPC分类号： H01L29/66583 ,  H01L21/2652 ,  H01L27/1203 ,  H01L29/66553 ,  H01L29/66772 ,  H01L29/78648

摘要： A method of fabricating a SOI semiconductor device with an implanted ground plane in the silicon substrate to increase the doping concentration underneath the channel region for suppressing short-channel effects (SCEs) such as drain-induced barrier lowering (DIBL). For a N-channel MOSFET, the implanted ground plane is P+ type such that if a P-type underlying substrate is used, the ground plane is automatically connected to ground potential (the substrate potential). For a SOI-type CMOS semiconductor device with two spaced-apart implanted ground planes each self-aligned to be underneath a corresponding channel region of the CMOS, two SOI-type MOSFET semiconductor devices of opposite conductivity types are formed on a same semiconductor substrate. The increase in doping concentration underneath the channel region prevents the electric field lines from the gate from terminating under the channel region; instead, the electric field lines terminate in the ground plane, thereby suppressing the short-channel effects and the off-state leakage current of the MOSFETs.

摘要翻译： 一种在硅衬底中制造具有注入接地面的SOI半导体器件的方法，以增加沟道区下方的掺杂浓度，以抑制诸如漏极诱导的势垒降低（DIBL）的短沟道效应（SCE）。 对于N沟道MOSFET，注入接地层是P +型，使得如果使用P型底层衬底，则接地层自动连接到接地电位（衬底电位）。 对于具有两个间隔开的注入接地层的SOI型CMOS半导体器件，其每个自对准位于CMOS的相应沟道区的下方，在同一半导体衬底上形成两个相反导电类型的SOI型MOSFET半导体器件。 通道区域下面的掺杂浓度的增加阻止了来自栅极的电场线在沟道区域下结束; 电场线终止于接地面，从而抑制MOSFET的短路效应和截止状态的漏电流。

公开(公告)号：US06359311B1

公开(公告)日：2002-03-19

申请号：US09761889

申请日：2001-01-17

申请人： Jean Pierre Colinge ,  Carlos H. Diaz

发明人： Jean Pierre Colinge ,  Carlos H. Diaz

IPC分类号： H01L2701

CPC分类号： H01L29/42384 ,  H01L29/66795 ,  H01L29/7854

摘要： The present invention discloses a method of fabricating a SOI semiconductor device with a quasi surrounding gate in the silicon substrate to increase the device current per unit device width, and allows better control over the short-channel effect and sub-threshold leakage. This method also enables fabrication of variable gate-length devices using conventional techniques compared to vertical/pillar transistors.

摘要翻译： 本发明公开了一种在硅衬底中制造具有准周围栅极的SOI半导体器件的方法，以增加每单位器件宽度的器件电流，并且允许更好地控制短沟道效应和次阈值泄漏。 与垂直/立柱晶体管相比，该方法还能够使用常规技术制造可变栅极长度器件。

公开(公告)号：US20140054724A1

公开(公告)日：2014-02-27

申请号：US13594190

申请日：2012-08-24

申请人： Kuo-Cheng Ching ,  Jean-Pierre Colinge ,  Zhiqiang Wu

发明人： Kuo-Cheng Ching ,  Jean-Pierre Colinge ,  Zhiqiang Wu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/42392 ,  H01L29/165 ,  H01L29/401 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/78696

摘要： Among other things, a semiconductor device comprising an aligned gate and a method for forming the semiconductor device are provided. The semiconductor device comprises a gate formed according to a multi-gate structure, such as a gate-all-around structure. A first gate portion of the gate is formed above a first channel of the semiconductor device. A second gate portion of the gate is formed below the first channel, and is aligned with the first gate portion. In an example of forming the gate, a cavity is etched within a semiconductor layer formed above a substrate. A dielectric layer is formed around at least some of the cavity to define a region of the cavity within which the second gate portion is to be formed in a self-aligned manner with the first gate portion. In this way, the semiconductor device comprises a first gate portion aligned with a second gate portion.

摘要翻译： 其中，提供了包括对准的栅极的半导体器件和用于形成半导体器件的方法。 半导体器件包括根据多门结构形成的栅极，例如栅极全绕结构。 栅极的第一栅极部分形成在半导体器件的第一沟道上方。 栅极的第二栅极部分形成在第一沟道下方，并与第一栅极部分对准。 在形成栅极的实例中，在形成于衬底上的半导体层内蚀刻空腔。 围绕至少一些空腔形成电介质层以限定空腔的区域，第二栅极部分将以其与第一栅极部分的自对准方式形成。 以这种方式，半导体器件包括与第二栅极部分对准的第一栅极部分。

公开(公告)号：US20120305893A1

公开(公告)日：2012-12-06

申请号：US13579825

申请日：2011-02-21

申请人： Jean-Pierre Colinge

发明人： Jean-Pierre Colinge

IPC分类号： H01L29/775 ,  H01L21/335

CPC分类号： H01L29/785 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78696 ,  H01L2029/7857

摘要： The invention provides transistor device comprising a source, a drain and a connecting channel, the channel is a nano-structure device adapted to allow current flow between the source and drain. The channel comprises an ultra-high doping concentration and is of the same polarity as in the source and/or drain. Essentially the transistor device of the present invention acts as a junctionless, highly-doped gated resistor. In the context of optimal performance of the transistor high doping means equal to or exceeds 1×1019 atom/cm3 results in that the device can operate as a junctionless transistor device.

摘要翻译： 本发明提供了包括源极，漏极和连接沟道的晶体管器件，该沟道是适于允许源极和漏极之间的电流流动的纳米结构器件。 该通道包括超高掺杂浓度并且具有与源极和/或漏极中相同的极性。 基本上本发明的晶体管器件用作无连接，高掺杂的门控电阻器。 在等于或超过1×1019原子/ cm3的晶体管高掺杂装置的最佳性能的上下文中，导致器件可以作为无连接晶体管器件工作。

公开(公告)号：US4810664A

公开(公告)日：1989-03-07

申请号：US896560

申请日：1986-08-14

申请人： Theodore I. Kamins ,  Jean-Pierre Colinge ,  Paul J. Marcoux ,  Lynn M. Roylance ,  John L. Moll

发明人： Theodore I. Kamins ,  Jean-Pierre Colinge ,  Paul J. Marcoux ,  Lynn M. Roylance ,  John L. Moll

IPC分类号： H01L27/12 ,  H01L21/265 ,  H01L21/266 ,  H01L21/336 ,  H01L21/762 ,  H01L29/78 ,  H01L21/76

CPC分类号： H01L21/76264 ,  H01L21/26533 ,  H01L21/266 ,  H01L21/76267 ,  H01L21/76281

摘要： A method for producing buried oxide layers in selected portions of a semiconductor substrate including the steps of applying a patterned mask made from a high-density material over a semiconductor substrate and selectively forming buried oxide layers by oxygen ion implantation. The high-density material of the mask is preferably tungsten, but can also be made from other suitable materials such as silicon nitride. A MOS transistor is made by the process of the present invention by applying the high-density mask material over the gate of the transistor, and forming buried oxide layers by ion implantation beneath only the source region and drain region of the transistor. The completed MOS transistor has the characteristics of reduced drain and source capacitance, reduced leakage, and faster response, but does not suffer from the floating-body effect of MOS transistors made by SOI processes.

摘要翻译： 一种用于在半导体衬底的选定部分中制造掩埋氧化物层的方法，包括以下步骤：将由高密度材料制成的图案化掩模施加在半导体衬底上，并通过氧离子注入选择性地形成掩埋氧化物层。 掩模的高密度材料优选为钨，但也可以由其它合适的材料如氮化硅制成。 通过在晶体管的栅极上施加高密度掩模材料，并且通过仅在晶体管的源极区域和漏极区域下的离子注入形成掩埋氧化物层，通过本发明的方法制造MOS晶体管。 完成的MOS晶体管具有降低的漏极和源极电容，减少的泄漏和更快的响应特性，但不受SOI工艺制造的MOS晶体管的浮体效应。

公开(公告)号：US09006829B2

公开(公告)日：2015-04-14

申请号：US13594190

申请日：2012-08-24

申请人： Jean-Pierre Colinge ,  Kuo-Cheng Ching ,  Zhiqiang Wu

发明人： Jean-Pierre Colinge ,  Kuo-Cheng Ching ,  Zhiqiang Wu

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/165 ,  H01L29/66

CPC分类号： H01L29/42392 ,  H01L29/165 ,  H01L29/401 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/78696

摘要： Among other things, a semiconductor device comprising an aligned gate and a method for forming the semiconductor device are provided. The semiconductor device comprises a gate formed according to a multi-gate structure, such as a gate-all-around structure. A first gate portion of the gate is formed above a first channel of the semiconductor device. A second gate portion of the gate is formed below the first channel, and is aligned with the first gate portion. In an example of forming the gate, a cavity is etched within a semiconductor layer formed above a substrate. A dielectric layer is formed around at least some of the cavity to define a region of the cavity within which the second gate portion is to be formed in a self-aligned manner with the first gate portion. In this way, the semiconductor device comprises a first gate portion aligned with a second gate portion.

摘要翻译： 其中，提供了包括对准的栅极的半导体器件和用于形成半导体器件的方法。 半导体器件包括根据多门结构形成的栅极，例如栅极全绕结构。 栅极的第一栅极部分形成在半导体器件的第一沟道上方。 栅极的第二栅极部分形成在第一沟道下方，并与第一栅极部分对准。 在形成栅极的实例中，在形成于衬底上的半导体层内蚀刻空腔。 围绕至少一些空腔形成电介质层以限定空腔的区域，第二栅极部分将以其与第一栅极部分的自对准方式形成。 以这种方式，半导体器件包括与第二栅极部分对准的第一栅极部分。

公开(公告)号：US08963206B2

公开(公告)日：2015-02-24

申请号：US13595232

申请日：2012-08-27

申请人： Jean-Pierre Colinge

发明人： Jean-Pierre Colinge

IPC分类号： H01L29/66

CPC分类号： H01L29/1054 ,  H01L29/66795 ,  H01L29/7851

摘要： The present disclosure is directed to a method of manufacturing a FinFET structure in which at least one initial set of fin structures is formed by photolithographic processes, followed by forming an additional fin structure by epitaxial growth of a semiconductor material between the initial set of fin structures. The method allows for formation of FinFET structures having increased fin density.

摘要翻译： 本公开涉及一种制造FinFET结构的方法，其中通过光刻工艺形成至少一组初始鳍片结构，然后通过半导体材料在初始翅片结构之间外延生长形成附加翅片结构 。 该方法允许形成具有增加的翅片密度的FinFET结构。

公开(公告)号：US20100276662A1

公开(公告)日：2010-11-04

申请号：US12753668

申请日：2010-04-02

申请人： Jean-Pierre Colinge

发明人： Jean-Pierre Colinge

IPC分类号： H01L29/78 ,  H01L29/775 ,  H01L21/336

CPC分类号： H01L29/785 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/66795 ,  H01L29/78696 ,  H01L2029/7857

摘要： A junctionless metal-oxide-semiconductor transistor is described. In one aspect, a transistor device comprises a semiconductor material. The semiconductor material comprises first, second, and third portions. The second portion is located between the first and third portions. The first, second, and third portions are doped with dopants of the same polarity and the same concentration. The transistor device further comprises an electrode connected to the second portion. A current flows between the first and third portions when a voltage is applied to the electrode.

摘要翻译： 描述了一种无连接的金属氧化物半导体晶体管。 在一个方面，晶体管器件包括半导体材料。 半导体材料包括第一，第二和第三部分。 第二部分位于第一和第三部分之间。 第一，第二和第三部分掺杂相同极性和相同浓度的掺杂剂。 晶体管器件还包括连接到第二部分的电极。 当电压施加到电极时，电流在第一和第三部分之间流动。

公开(公告)号：US4857476A

公开(公告)日：1989-08-15

申请号：US148419

申请日：1988-01-26

申请人： Jean-Pierre Colinge

发明人： Jean-Pierre Colinge

IPC分类号： H01L29/73 ,  H01L21/31 ,  H01L21/331 ,  H01L21/74 ,  H01L29/732

CPC分类号： H01L29/66272 ,  H01L21/743 ,  Y10S148/01 ,  Y10S148/011

摘要： An improved method for fabricating a bipolar transistor reduces base current resistance which heretofore has limited the switching frequency and current handling ability of bipolar transistors. The transistor base and emitter are formed as a diffusion through an emitter contact pedestal formed on an epitaxial layer over a substrate. Access to the n-type emitter is through the emitter contact pedestal while access to the lightly doped p-type base is through a nearby heavily doped p-type base insert. Electrical isolation between the pedestal and the base insert is ensured by forming oxide sidewall spacers on the emitter contact pedestal during the implant used to form the base insert. Defining the isolation with sidewall spacers permits reliable isolation of emitter and base insert while minimizing their physical separation. The minimized physical separation provides a base current path with considerably less total resistance than is found in the background art in which the isolation is defined photo-lithographically.

公开(公告)号：US4725561A

公开(公告)日：1988-02-16

申请号：US882901

申请日：1986-06-05

申请人： Michel Haond ,  Jean-Pierre Colinge ,  Daniel Bensahel ,  Didier Dutartre

发明人： Michel Haond ,  Jean-Pierre Colinge ,  Daniel Bensahel ,  Didier Dutartre

IPC分类号： H01L21/20 ,  H01L21/762 ,  H01L21/263 ,  H01L21/76 ,  H01L21/95

CPC分类号： H01L21/76264 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/02667 ,  H01L21/76272

摘要： This process consists of producing patterns (17) of an insulating material on a monocrystalline silicon substrate (12), depositing on the complete structure an amorphous or polycrystalline silicon film (26), covering the latter with a layer (28) of an encapsulating material, carrying out a heat treatment on the structure obtained serving to vertically embed in substrate (12) the insulating material patterns (17) and forming above the latter a monocrystalline silicon layer (33), eliminating the encapsulating material layer (28) and etching the monocrystalline silicon layer obtained (33), so as to form said islands (34).

摘要翻译： PCT No.PCT / FR85 / 00270 Sec。 371日期：1986年6月5日 102（e）日期1986年6月5日PCT归档1985年10月1日PCT公布。 出版物WO86 / 02198 日期为1986年4月10日。该方法包括在单晶硅衬底（12）上产生绝缘材料的图案（17），在完整结构上沉积无定形或多晶硅膜（26），用层 （28），对用于垂直地嵌入基板（12）中的绝缘材料图案（17）获得的结构进行热处理，并在其上形成单晶硅层（33），消除封装材料 层（28），并蚀刻获得的单晶硅层（33），以形成所述岛（34）。