公开(公告)号：US20240381545A1

公开(公告)日：2024-11-14

申请号：US18207224

申请日：2023-06-08

Applicant: JIN MOON NOH

Inventor： JIN MOON NOH

IPC: H05K5/00 ,  G01D11/24 ,  H04R1/04 ,  H05K5/02

Abstract: A fault diagnostic apparatus may include an upper case with a bottom having an opening, a lower case coupled to the bottom of the upper case, and a printed circuit board (PCB) substrate module including a substrate supported on an inner side of the upper case or the lower case, and a microphone disposed in the substrate adjacent to the vibration plate to generate a sensing signal of an acoustic wave by the vibration generated from the vibration plate. The lower case may have a vibration plate formed toward the upper case on a lower surface and be configured to vibrate itself in response to an external vibration.

公开(公告)号：US20230184312A1

公开(公告)日：2023-06-15

申请号：US17924353

申请日：2021-06-11

Applicant: Kyoung Jin MOON

Inventor： Kyoung Jin MOON

IPC: F16H9/12 ,  F16H55/56

CPC classification number: F16H9/125 ,  F16H55/56

Abstract: A variable pitch pulley includes a rotary shaft, a fixed sheave fixed to the rotary shaft, and a moving sheave forming a belt groove with the fixed sheave. The moving sheave includes an inner sheave and an outer sheave radially stacked on the inner sheave. The pitch pulley further includes a moving sheave-positing unit determining relative positions of the inner and outer sheaves. The inner and outer sheaves are simultaneously moved in an axial direction of the rotary shaft in a first moving mode, and only the outer sheave is moved in the axial direction in a second moving mode.

公开(公告)号：US20190182298A1

公开(公告)日：2019-06-13

申请号：US16280832

申请日：2019-02-20

Applicant: Byung Jin MOON

Inventor： Byung Jin MOON

IPC: H04L29/06

Abstract: Disclosed is a method for supporting a real-time lecture on any subject via telephone, in which if an instructor expresses, via a terminal, an intention to currently provide a lecture to a list of lecture available subjects that have been previously registered: a process of measuring an expected quality of media traffic between anInternet telephone server and an instructor terminal and quantifying and storing the same is added, and if a student who wants a real-time lecture on any subject chooses an instructor from a list of currently lecture available instructors for the subject in accordance with an expected telephone call quality or his/her preferences, and requests a real-time lecture with simple additional information such as a subject or a lecture time, the instructor accepts the lecture after confirming the additional information; before performing an actual telephone connection, an expected quality of the media traffic between the instructor terminal and a student terminal is measured, and when the expected quality is below a predetermined reference value, the instructor and the student are notified, and when the expected quality meets the reference value or the instructor and the student agree, it is supported to connect a telephone for a real-time lecture between the instructor and the student; and in the case of an ordinary telephone, only an actual telephone connection is supported.

公开(公告)号：US09691684B2

公开(公告)日：2017-06-27

申请号：US14327558

申请日：2014-07-09

Applicant: Jae-hwa Park ,  Sung-hee Kang ,  Kwang-jin Moon ,  Byung-lyul Park ,  Suk-chul Bang

Inventor： Jae-hwa Park ,  Sung-hee Kang ,  Kwang-jin Moon ,  Byung-lyul Park ,  Suk-chul Bang

IPC: H01L27/108 ,  H01L23/48 ,  H01L49/02 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L28/90 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: An integrated circuit device is provided which includes a through-silicon via (TSV) structure and one or more decoupling capacitors, along with a method of manufacturing the same. The integrated circuit device may include a semiconductor structure including a semiconductor substrate, a TSV structure passing through the semiconductor substrate, and a decoupling capacitor formed in the semiconductor substrate and connected to the TSV structure. The TSV structure and the one or more decoupling capacitors may be substantially simultaneously formed. A plurality of decoupling capacitors may be disposed within a keep out zone (KOZ) of the TSV structure. The plurality of decoupling capacitors may have the same or different widths and/or depths. An isopotential conductive layer may be formed to reduce or eliminate a potential difference between different parts of the TSV structure.

公开(公告)号：US09431889B2

公开(公告)日：2016-08-30

申请号：US13219842

申请日：2011-08-29

Applicant: Dong Zo Kim ,  Young Tack Hong ,  Jin Sung Choi ,  Young Jin Moon ,  Sang Wook Kwon ,  Yun Kwon Park ,  Chang Sik Yoo ,  Eun Seok Park ,  Ki Young Kim ,  Young Ho Ryu ,  Nam Yun Kim ,  Yong Seong Roh

Inventor： Dong Zo Kim ,  Young Tack Hong ,  Jin Sung Choi ,  Young Jin Moon ,  Sang Wook Kwon ,  Yun Kwon Park ,  Chang Sik Yoo ,  Eun Seok Park ,  Ki Young Kim ,  Young Ho Ryu ,  Nam Yun Kim ,  Yong Seong Roh

IPC: H02M7/217 ,  H02M1/08

CPC classification number: H02M1/083 ,  H02M7/217

Abstract: An active rectifier and a wireless power receiver including the active rectifier are provided. According to an aspect, an active rectifier may include: a first loop configured to provide voltage when the phase of an input signal is positive; and a second loop configured to provide voltage when the phase of the input signal is negative, wherein the first loop and the second loop include a delay locked loop configured to compensate for reverse current leakage due to a delay of a switch included therein.

Abstract translation: 提供了包括有源整流器的有源整流器和无线电力接收器。 根据一方面，有源整流器可以包括：第一回路，其被配置为当输入信号的相位为正时提供电压; 以及第二回路，其被配置为当所述输入信号的相位为负时提供电压，其中所述第一回路和所述第二回路包括被配置为补偿由于其中包括的开关的延迟引起的反向电流泄漏的延迟锁定回路。

公开(公告)号：US09379042B2

公开(公告)日：2016-06-28

申请号：US14504647

申请日：2014-10-02

Applicant: Jae-Hwa Park ,  Suk-Chul Bang ,  Byung-Lyul Park ,  Kwang-Jin Moon

Inventor： Jae-Hwa Park ,  Suk-Chul Bang ,  Byung-Lyul Park ,  Kwang-Jin Moon

IPC: H01L21/02 ,  H01L23/48 ,  H01L49/02 ,  H01L21/768 ,  H01L27/108 ,  H01L23/522 ,  H01L23/538

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/522 ,  H01L23/5384 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/87 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit device is provided. The integrated circuit device includes: a capacitor including an electrode formed in a first area on a substrate; a through-silicon-via (TSV) landing pad formed in a second area on the substrate, the TSV landing pad including the same material as the electrode; a multi-layered interconnection structure formed on the capacitor and the TSV landing pad; and a TSV structure passing through the substrate, the TSV structure being connected to the multi-layered interconnection structure through the TSV landing pad.

Abstract translation: 提供集成电路装置。 集成电路装置包括：电容器，包括形成在基板上的第一区域中的电极; 形成在所述基板上的第二区域中的通硅通孔（TSV）着陆焊盘，所述TSV着陆焊盘包括与所述电极相同的材料; 形成在电容器和TSV着陆板上的多层互连结构; TSV结构通过基板，TSV结构通过TSV着陆焊盘连接到多层互连结构。

公开(公告)号：US09263624B2

公开(公告)日：2016-02-16

申请号：US13643422

申请日：2011-04-05

Applicant: Sang Jin Moon ,  Won Wook So ,  Myung Hoee Koo ,  Dong Soon Park

Inventor： Sang Jin Moon ,  Won Wook So ,  Myung Hoee Koo ,  Dong Soon Park

IPC: H01L31/00 ,  H01L31/18 ,  C30B17/00 ,  C30B11/00 ,  C30B28/06 ,  C30B29/06

CPC classification number: H01L31/182 ,  C30B11/002 ,  C30B11/003 ,  C30B17/00 ,  C30B28/06 ,  C30B29/06 ,  Y02E10/546 ,  Y02P70/521

Abstract: The present invention relates to a high-output apparatus for manufacturing a polycrystal silicon ingot for a solar cell, and more particularly, to an apparatus for manufacturing a polycrystal silicon ingot by means of heating and melting raw silicon in a vacuum chamber, and then cooling the molten silicon, wherein the apparatus comprises: a plurality of crucibles arranged so as to be horizontally separated from one another within the vacuum chamber, and in each of which raw silicon is filled for manufacturing polycrystal silicon ingots; heating means provided at the outside of each of the crucibles so as to heat each crucible and melt the raw silicon filled therein; and cooling means for cooling the crucibles, so as to enable the silicon melted by the heating means to be cooled in one direction and be formed into polycrystal ingots.

Abstract translation: 本发明涉及一种用于制造太阳能电池用多晶硅锭的高输出装置，更具体地，涉及一种通过在真空室中加热和熔化原料硅然后冷却而制造多晶硅锭的装置 所述熔融硅，其中所述装置包括：多个坩埚，其布置成在所述真空室内彼此水平分离，并且其中每个所述原料硅被填充以制造多晶硅锭; 设置在每个坩埚的外侧的加热装置，以加热每个坩埚并熔化填充在其中的原料硅; 以及用于冷却坩埚的冷却装置，以使由加热装置熔化的硅在一个方向上被冷却并形成多晶锭。

公开(公告)号：US09142490B2

公开(公告)日：2015-09-22

申请号：US14325335

申请日：2014-07-07

Applicant: Jae-hwa Park ,  Kwang-jin Moon ,  Byung-lyul Park ,  Suk-chul Bang

Inventor： Jae-hwa Park ,  Kwang-jin Moon ,  Byung-lyul Park ,  Suk-chul Bang

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/53295 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Provided is an integrated circuit device including a through-silicon-via (TSV) structure and a method of manufacturing the integrated circuit device. The integrated circuit device includes a semiconductor structure including a substrate and an interlayer insulating film, a TSV structure passing through the substrate and the interlayer insulating film, a via insulating film substantially surrounding the TSV structure, and an insulating spacer disposed between the interlayer insulating film and the via insulating film.

Abstract translation: 提供了一种包括贯穿硅通孔（TSV）结构的集成电路器件以及集成电路器件的制造方法。 集成电路装置包括：半导体结构，包括基板和层间绝缘膜，通过基板的TSV结构和层间绝缘膜，基本上包围TSV结构的通孔绝缘膜，以及设置在层间绝缘膜 和通孔绝缘膜。

公开(公告)号：US09018768B2

公开(公告)日：2015-04-28

申请号：US13627790

申请日：2012-09-26

Applicant: Byung-lyul Park ,  Gil-heyun Choi ,  Suk-chul Bang ,  Kwang-jin Moon ,  Dong-chan Lim ,  Deok-young Jung

Inventor： Byung-lyul Park ,  Gil-heyun Choi ,  Suk-chul Bang ,  Kwang-jin Moon ,  Dong-chan Lim ,  Deok-young Jung

IPC: H01L23/48 ,  H01L23/02 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L21/76898 ,  H01L21/76801 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565

Abstract: A semiconductor device includes a circuit pattern over a first surface of a substrate, an insulating interlayer covering the circuit pattern, a TSV structure filling a via hole through the insulating interlayer and the substrate, an insulation layer structure on an inner wall of the via hole and on a top surface of the insulating interlayer, a buffer layer on the TSV structure and the insulation layer structure, a conductive structure through the insulation layer structure and a portion of the insulating interlayer to be electrically connected to the circuit pattern, a contact pad onto a bottom of the TSV structure, and a protective layer structure on a second surface the substrate to surround the contact pad.

Abstract translation: 半导体器件包括在衬底的第一表面上的电路图案，覆盖电路图案的绝缘夹层，填充通过绝缘夹层和衬底的通孔的TSV结构，在通孔的内壁上的绝缘层结构 并且在绝缘中间层的上表面上，具有TSV结构和绝缘层结构的缓冲层，通过绝缘层结构的导电结构和电连接到电路图案的绝缘夹层的一部分，接触垫 到TSV结构的底部，以及在第二表面上的保护层结构，以包围接触垫。

公开(公告)号：US20150108605A1

公开(公告)日：2015-04-23

申请号：US14504647

申请日：2014-10-02

Applicant: Jae-Hwa Park ,  Suk-Chul Bang ,  Byung-Lyul Park ,  Kwang-Jin Moon

Inventor： Jae-Hwa Park ,  Suk-Chul Bang ,  Byung-Lyul Park ,  Kwang-Jin Moon

IPC: H01L23/50 ,  H01L49/02 ,  H01L27/108 ,  H01L23/48

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/522 ,  H01L23/5384 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/87 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit device is provided. The integrated circuit device includes: a capacitor including an electrode formed in a first area on a substrate; a through-silicon-via (TSV) landing pad formed in a second area on the substrate, the TSV landing pad including the same material as the electrode; a multi-layered interconnection structure formed on the capacitor and the TSV landing pad; and a TSV structure passing through the substrate, the TSV structure being connected to the multi-layered interconnection structure through the TSV landing pad.

Abstract translation: 提供集成电路装置。 集成电路装置包括：电容器，包括形成在基板上的第一区域中的电极; 形成在所述基板上的第二区域中的通硅通孔（TSV）着陆焊盘，所述TSV着陆焊盘包括与所述电极相同的材料; 形成在电容器和TSV着陆板上的多层互连结构; TSV结构通过基板，TSV结构通过TSV着陆焊盘连接到多层互连结构。