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    Method of forming semiconductor device
    1.
    发明授权
    Method of forming semiconductor device 有权
    半导体器件形成方法

    公开(公告)号：US08546256B2

    公开(公告)日：2013-10-01

    申请号：US13167225

    申请日：2011-06-23

    申请人： Deok-young Jung ,  Gil-heyun Choi ,  Suk-chul Bang ,  Byung-lyul Park ,  Kwang-jin Moon ,  Dong-chan Lim

    发明人： Deok-young Jung ,  Gil-heyun Choi ,  Suk-chul Bang ,  Byung-lyul Park ,  Kwang-jin Moon ,  Dong-chan Lim

    IPC分类号： H01L21/283

    CPC分类号： H01L21/76802 ,  H01L21/02057 ,  H01L21/30655 ,  H01L21/76898

    摘要： The methods include forming a semiconductor substrate pattern by etching a semiconductor substrate. The semiconductor pattern has a first via hole that exposes side walls of the semiconductor substrate pattern, and the side walls of the semiconductor substrate pattern exposed by the first via hole have an impurity layer pattern. The methods further include treating upper surfaces of the semiconductor substrate pattern, the treated upper surfaces of the semiconductor substrate pattern being hydrophobic; removing the impurity layer pattern from the side walls of the semiconductor substrate pattern exposed by the first via hole; forming a first insulating layer pattern on the side walls of the semiconductor substrate pattern exposed by the first via hole; and filling a first conductive layer pattern into the first via hole and over the first insulating layer pattern.

    摘要翻译： 所述方法包括通过蚀刻半导体衬底形成半导体衬底图案。 半导体图案具有暴露半导体衬底图案的侧壁的第一通孔，并且由第一通孔露出的半导体衬底图案的侧壁具有杂质层图案。 所述方法还包括处理半导体衬底图案的上表面，所处理的半导体衬底图案的上表面是疏水的; 从由第一通孔露出的半导体衬底图案的侧壁去除杂质层图案; 在由第一通孔露出的半导体衬底图案的侧壁上形成第一绝缘层图案; 以及将第一导电层图案填充到第一通孔中并在第一绝缘层图案之上。

    METHOD OF FORMING SEMICONDUCTOR DEVICE
    3.
    发明申请
    METHOD OF FORMING SEMICONDUCTOR DEVICE 有权
    形成半导体器件的方法

    公开(公告)号：US20110318922A1

    公开(公告)日：2011-12-29

    申请号：US13167225

    申请日：2011-06-23

    申请人： Deok-young Jung ,  Gil-heyun Choi ,  Suk-chul Bang ,  Byung-lyul Park ,  Kwang-jin Moon ,  Dong-chan Lim

    发明人： Deok-young Jung ,  Gil-heyun Choi ,  Suk-chul Bang ,  Byung-lyul Park ,  Kwang-jin Moon ,  Dong-chan Lim

    IPC分类号： H01L21/283

    CPC分类号： H01L21/76802 ,  H01L21/02057 ,  H01L21/30655 ,  H01L21/76898

    摘要： The methods include forming a semiconductor substrate pattern by etching a semiconductor substrate. The semiconductor pattern has a first via hole that exposes side walls of the semiconductor substrate pattern, and the side walls of the semiconductor substrate pattern exposed by the first via hole have an impurity layer pattern. The methods further include treating upper surfaces of the semiconductor substrate pattern, the treated upper surfaces of the semiconductor substrate pattern being hydrophobic; removing the impurity layer pattern from the side walls of the semiconductor substrate pattern exposed by the first via hole; forming a first insulating layer pattern on the side walls of the semiconductor substrate pattern exposed by the first via hole; and filling a first conductive layer pattern into the first via hole and over the first insulating layer pattern.

    摘要翻译： 所述方法包括通过蚀刻半导体衬底形成半导体衬底图案。 半导体图案具有暴露半导体衬底图案的侧壁的第一通孔，并且由第一通孔露出的半导体衬底图案的侧壁具有杂质层图案。 所述方法还包括处理半导体衬底图案的上表面，所处理的半导体衬底图案的上表面是疏水的; 从由第一通孔露出的半导体衬底图案的侧壁去除杂质层图案; 在由第一通孔露出的半导体衬底图案的侧壁上形成第一绝缘层图案; 以及将第一导电层图案填充到第一通孔中并在第一绝缘层图案之上。

    INTEGRATED CIRCUIT DEVICE INCLUDING THROUGH-SILICON VIA STRUCTURE HAVING OFFSET INTERFACE
    7.
    发明申请
    INTEGRATED CIRCUIT DEVICE INCLUDING THROUGH-SILICON VIA STRUCTURE HAVING OFFSET INTERFACE 有权
    集成电路设备，通过具有偏移接口的结构，包括硅

    公开(公告)号：US20130119547A1

    公开(公告)日：2013-05-16

    申请号：US13603978

    申请日：2012-09-05

    申请人： Su-kyoung Kim ,  Gil-heyun Choi ,  Byung-Iyul Park ,  Kwang-jin Moon ,  Kun-sang Park ,  Dong-chan Lim ,  Do-sun Lee

    发明人： Su-kyoung Kim ,  Gil-heyun Choi ,  Byung-Iyul Park ,  Kwang-jin Moon ,  Kun-sang Park ,  Dong-chan Lim ,  Do-sun Lee

    IPC分类号： H01L23/532 ,  H01L23/498

    CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2924/13091 ,  H01L2924/00

    摘要： An integrated circuit device includes a substrate through which a first through-hole extends, and an interlayer insulating film on the substrate, the interlayer insulating film having a second through-hole communicating with the first through-hole. A Through-Silicon Via (TSV) structure is provided in the first through-hole and the second through-hole. The TSV structure extends to pass through the substrate and the interlayer insulating film. The TSV structure comprises a first through-electrode portion having a top surface located in the first through-hole, and a second through-electrode portion having a bottom surface contacting with the top surface of the first through-electrode portion and extending from the bottom surface to at least the second through-hole. Related fabrication methods are also described.

    摘要翻译： 集成电路器件包括：第一通孔延伸穿过的衬底和衬底上的层间绝缘膜，所述层间绝缘膜具有与第一通孔连通的第二通孔。 在第一通孔和第二通孔中设置有硅通孔（TSV）结构。 TSV结构延伸穿过衬底和层间绝缘膜。 TSV结构包括具有位于第一通孔中的顶表面的第一通电极部分和具有与第一贯穿电极部分的顶表面接触并从底部延伸的底表面的第二通电极部分 表面至少到第二通孔。 还描述了相关的制造方法。

    Semiconductor device including fuse
    10.
    发明授权
    Semiconductor device including fuse 有权
    半导体装置包括保险丝

    公开(公告)号：US08044490B2

    公开(公告)日：2011-10-25

    申请号：US12502490

    申请日：2009-07-14

    申请人： Seung-woo Shin ,  Byung-lyul Park ,  Jong-myeong Lee ,  Gil-heyun Choi ,  Jong-ho Yun

    发明人： Seung-woo Shin ,  Byung-lyul Park ,  Jong-myeong Lee ,  Gil-heyun Choi ,  Jong-ho Yun

    IPC分类号： H01L29/00 ,  H01L27/10

    CPC分类号： H01L23/5258 ,  H01L27/105 ,  H01L27/10894 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided is a semiconductor device including a fuse, in which a insulating layer surrounding the fuse or metal wiring is prevented from being damaged due to the cut of a fuse, which can occur when a repair process is performed. The semiconductor device includes a conductive line formed on a semiconductor layer, a protective layer formed on the conductive line, one or more fuses that are electrically connected to the conductive line, and a fuse protective layer formed on the one or more fuses, and spaced apart from the protective layer.

    摘要翻译： 提供了一种包括保险丝的半导体器件，其中防止在保险丝或金属布线周围的绝缘层由于保险丝的切断而被损坏，这在维修过程中可能发生。 半导体器件包括形成在半导体层上的导电线，形成在导电线上的保护层，与导电线电连接的一个或多个保险丝，以及形成在一个或多个保险丝上的保险丝保护层， 除了保护层。