公开(公告)号：US20160183374A1

公开(公告)日：2016-06-23

申请号：US14575775

申请日：2014-12-18

申请人： Mani Prakash ,  Thomas T. Holden ,  Jeffory L. Smalley ,  Ram S. Viswanath ,  Bassam N. Coury ,  Dimitrios Ziakas ,  Chong J. Zhao ,  Jonathan W. Thibado ,  Gregorio R. Murtagian ,  Kuang C. Liu ,  Rajasekaran Swaminathan ,  Zhichao Zhang ,  John M. Lynch ,  David J. Llapitan ,  Sanka Ganesan ,  Xiang Li ,  George Vergis

发明人： Mani Prakash ,  Thomas T. Holden ,  Jeffory L. Smalley ,  Ram S. Viswanath ,  Bassam N. Coury ,  Dimitrios Ziakas ,  Chong J. Zhao ,  Jonathan W. Thibado ,  Gregorio R. Murtagian ,  Kuang C. Liu ,  Rajasekaran Swaminathan ,  Zhichao Zhang ,  John M. Lynch ,  David J. Llapitan ,  Sanka Ganesan ,  Xiang Li ,  George Vergis

IPC分类号： H05K1/18 ,  H01R12/72 ,  H05K1/11 ,  H05K1/02 ,  H05K3/30 ,  H05K3/34

CPC分类号： H05K1/181 ,  H01L23/00 ,  H01L23/498 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01R12/712 ,  H01R12/79 ,  H05K2201/10159 ,  H05K2201/10325 ,  Y02P70/611

摘要： Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.

摘要翻译： 公开了可配置的中央处理单元（CPU）封装基板。 描述了包括处理设备接口的封装衬底。 封装衬底还包括设置在封装衬底上的存储器件电接口。 封装衬底还包括靠近存储器件电接口设置的可移除存储器机械接口。 可移除存储器机械接口是允许在将存储器件附接到封装衬底之后容易地从封装衬底移除存储器件。

公开(公告)号：US20170179066A1

公开(公告)日：2017-06-22

申请号：US14974881

申请日：2015-12-18

申请人： Russell S. Aoki ,  John W. Jaeger ,  Michael S. Brazel ,  Daniel P. Carter ,  Anthony P. Valpiani ,  Michael R. Hui ,  Rashelle Yee ,  Joseph J. Jasniewski ,  Shelby A. Ferguson ,  Thomas A. Boyd ,  Jonathan W. Thibado ,  Penny K. Woodcock ,  Rachel G. Taylor ,  Laura S. Mortimer

发明人： Russell S. Aoki ,  John W. Jaeger ,  Michael S. Brazel ,  Daniel P. Carter ,  Anthony P. Valpiani ,  Michael R. Hui ,  Rashelle Yee ,  Joseph J. Jasniewski ,  Shelby A. Ferguson ,  Thomas A. Boyd ,  Jonathan W. Thibado ,  Penny K. Woodcock ,  Rachel G. Taylor ,  Laura S. Mortimer

IPC分类号： H01L23/00 ,  B23K3/02

CPC分类号： B23K3/029 ,  H01L2924/15311

摘要： Reflow Grid Array technology may be implemented on an interposer device, where the interposer is placed between a motherboard and a BGA package. The interposer may provide a controlled heat source to reflow solder between the interposer and the BGA package. A technical problem faced by an interposer using RGA technology is solder cleaning and removal when removing a BGA package. Technical solutions described herein provide processes and equipment for bulk solder removal from a BGA package that can be executed in the field.

公开(公告)号：US20160190716A1

公开(公告)日：2016-06-30

申请号：US14583357

申请日：2014-12-26

申请人： Kuang Liu ,  Gregorio Murtagian ,  David J. Llapitan ,  Jeffory L. Smalley ,  Gaurav Chawla ,  Joshua D. Heppner ,  Vijaykumar Krithivasan ,  Jonathan W. Thibado

发明人： Kuang Liu ,  Gregorio Murtagian ,  David J. Llapitan ,  Jeffory L. Smalley ,  Gaurav Chawla ,  Joshua D. Heppner ,  Vijaykumar Krithivasan ,  Jonathan W. Thibado

IPC分类号： H01R12/70 ,  H01R43/20

CPC分类号： H01R12/89 ,  H01R12/716 ,  H05K7/1007

摘要： Some forms relate to a socket having a housing. A first receiving pin field is formed as part of the housing. The first pin receiving field includes a first plurality of electrical contacts. A second receiving pin field is formed as part of the housing. The second pin field includes a second plurality of electrical contacts. An actuation mechanism is configured to engage the first plurality electrical contacts with a first set of pins on a first electronic package and the second plurality electrical contacts with a second set of pins on a second electronic package.

摘要翻译： 一些形式涉及具有外壳的插座。 第一接收引脚字段形成为外壳的一部分。 第一引脚接收区域包括第一多个电触点。 第二接收引脚字段形成为外壳的一部分。 第二引脚字段包括第二多个电触点。 致动机构构造成使第一多个电触点与第一电子封装上的第一组引脚接合，而第二多个电触点与第二电子封装上的第二组引脚接合。

公开(公告)号：US20160190717A1

公开(公告)日：2016-06-30

申请号：US14583372

申请日：2014-12-26

申请人： David J. Llapitan ,  Jeffory L. Smalley ,  Gaurav Chawla ,  Joshua D. Heppner ,  Vijaykumar Krithivasan ,  Jonathan W. Thibado ,  Kuang Liu ,  Gregorio Murtagian

发明人： David J. Llapitan ,  Jeffory L. Smalley ,  Gaurav Chawla ,  Joshua D. Heppner ,  Vijaykumar Krithivasan ,  Jonathan W. Thibado ,  Kuang Liu ,  Gregorio Murtagian

IPC分类号： H01R12/70 ,  H01R43/20

CPC分类号： H05K7/1084

摘要： Some forms relate to an electronic assembly that includes a plurality of electronic package. The electronic assembly includes a frame and a first electronic package mounted on the frame. The first electronic package includes a first pin grid array. The electronic assembly further includes a second electronic package mounted on the frame. The second electronic package includes a second pin grid array. The electronic assembly further includes an actuation mechanism on the frame. The actuation mechanism is configured to move the first electronic package and the second electronic package relative to the frame during operation of the actuation mechanism.

摘要翻译： 一些形式涉及包括多个电子封装的电子组件。 电子组件包括安装在框架上的框架和第一电子封装件。 第一电子封装包括第一引脚格栅阵列。 电子组件还包括安装在框架上的第二电子封装。 第二电子封装包括第二引脚格栅阵列。 电子组件还包括在框架上的致动机构。 致动机构构造成在致动机构的操作期间相对于框架移动第一电子封装和第二电子封装。