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    ADAPTIVE VOLTAGE INPUT TO A CHARGE PUMP
    3.
    发明申请
    ADAPTIVE VOLTAGE INPUT TO A CHARGE PUMP 有权
    自适应电压输入到充电泵

    公开(公告)号：US20140192607A1

    公开(公告)日：2014-07-10

    申请号：US13976791

    申请日：2012-05-08

    申请人： Kuljit Bains ,  George Vergis

    发明人： Kuljit Bains ,  George Vergis

    IPC分类号： G11C5/14

    CPC分类号： G11C5/145 ,  G11C11/4074 ,  G11C29/021 ,  G11C29/028

    摘要： A memory subsystem includes an adaptive output voltage to provide a voltage based on a power profile of a memory device of the memory subsystem. A charge pump increases the voltage to a level needed to write data to the memory device. The voltage provided is based on the power profile of the memory device, which indicates a voltage level that provides good efficiency for the charge pump, and is within maximum levels for the memory device. The voltage can be higher than a nominal voltage indicated for the memory device in a specification.

    摘要翻译： 存储器子系统包括自适应输出电压，以基于存储器子系统的存储器件的功率曲线来提供电压。 电荷泵将电压提高到将数据写入存储器件所需的水平。 所提供的电压基于存储器件的功率曲线，其指示为电荷泵提供良好效率的电压电平，并且在存储器件的最大电平内。 电压可以高于规范中为存储器件指示的额定电压。

    DELAY-COMPENSATED ERROR INDICATION SIGNAL
    4.
    发明申请
    DELAY-COMPENSATED ERROR INDICATION SIGNAL 有权
    延迟补偿错误指示信号

    公开(公告)号：US20140013168A1

    公开(公告)日：2014-01-09

    申请号：US13997850

    申请日：2012-03-31

    申请人： Kuljit Singh Bains ,  George Vergis

    发明人： Kuljit Singh Bains ,  George Vergis

    IPC分类号： G06F11/10

    CPC分类号： G06F11/10 ,  G06F11/108 ,  G11C5/04 ,  G11C7/1063 ,  G11C29/42 ,  G11C29/44 ,  G11C2029/0409 ,  G11C2029/0411

    摘要： A memory subsystem has multiple memory devices coupled to a command/address line and an error alert line, the error alert line delay-compensated to provide deterministic alert signal timing. The command/address line and the error alert line are connected between the memory devices and a memory controller that manages the memory devices. The command/address line is driven by the memory controller, and the error alert line is driven by the memory devices.

    摘要翻译： 存储器子系统具有耦合到命令/地址线和错误警报线的多个存储器件，误差警报线被延迟补偿以提供确定性警报信号定时。 命令/地址线和错误警报线连接在存储器件和管理存储器件的存储器控​​制器之间。 命令/地址线由存储器控制器驱动，错误警报线由存储器件驱动。

    METHOD TO STAGGER SELF REFRESHES
    5.
    发明申请
    METHOD TO STAGGER SELF REFRESHES 有权
    自动刷新的方法

    公开(公告)号：US20110252193A1

    公开(公告)日：2011-10-13

    申请号：US12758667

    申请日：2010-04-12

    申请人： Kuljit S. Bains ,  George Vergis

    发明人： Kuljit S. Bains ,  George Vergis

    IPC分类号： G06F12/00

    CPC分类号： G11C11/406 ,  G11C11/40611

    摘要： A system, device, and method for designating a first rank among a plurality of memory ranks of a Memory Module as a primary rank and a second one or more ranks as secondary ranks, triggering, via hardware logic internal to the Memory Module coupled with the plurality of memory ranks, a refresh of the primary rank at a first time (e.g., Time1), and triggering a non overlapping staggered refresh of each of the secondary ranks at a second one or more times (e.g., Time2 through Timen) corresponding to each of the respective memory ranks designated as the secondary ranks.

    摘要翻译： 一种用于将作为主等级的存储器模块的多个存储器级别中的第一级指定为第二级别的第二级别的系统，设备和方法，并且经由与存储器模块耦合的存储器模块内部的硬件逻辑触发， 多个存储器等级，第一次刷新主等级（例如，Time1），并且在第二次或更多次（例如，Time2至Timen）触发每个次级队列的非重叠交错刷新，对应于 每个相应的记忆级别被指定为次级排名。

    Memory having swizzled signal lines
    6.
    发明申请
    Memory having swizzled signal lines 审中-公开
    存储器有信号线

    公开(公告)号：US20070005836A1

    公开(公告)日：2007-01-04

    申请号：US11148160

    申请日：2005-06-07

    申请人： Sandeep Jain ,  George Vergis ,  John Halbert ,  Nilesh Shah

    发明人： Sandeep Jain ,  George Vergis ,  John Halbert ,  Nilesh Shah

    IPC分类号： G06F13/38

    CPC分类号： G06F13/4013 ,  G11C5/06 ,  G11C7/04 ,  G11C7/1006 ,  G11C8/20

    摘要： Swizzle information for signal lines on a memory component may be stored on the memory component. The swizzle information may be transmitted to a memory controller which may include logic to receive the swizzle information which is then used to deswizzle data received from the memory component. Data may be transmitted from a memory device to a memory controller in a format that is tolerant of swizzling on signal lines between the device and the controller. The format may include codes having unique of numbers of values. Data may be sent in multi-code bursts that divide a data range into progressively smaller ranges. Other embodiments are described and claimed.

    摘要翻译： 存储器组件上的信号线的交换信息可以存储在存储器组件上。 交换信息可以被发送到存储器控制器，存储器控制器可以包括用于接收转移信息的逻辑，然后用于去除从存储器组件接收的数据。 数据可以以容许在设备和控制器之间的信号线上进行转换的格式从存储器件发送到存储器控制器。 该格式可以包括具有唯一值的值的代码。 可以以将多个数字范围分割成逐渐变小的多码脉冲串来发送数据。 描述和要求保护其他实施例。

    Integrated RAM thermal sensor
    7.
    发明授权
    Integrated RAM thermal sensor 有权
    集成RAM热传感器

    公开(公告)号：US06453218B1

    公开(公告)日：2002-09-17

    申请号：US09280913

    申请日：1999-03-29

    申请人： George Vergis

    发明人： George Vergis

    IPC分类号： G05D2300

    CPC分类号： G05D23/20 ,  G05D23/1917

    摘要： A method and apparatus for the thermal sensing and regulating of a RAM device using temperature sensing circuitry, embedded directly in the device, is presented. A predetermined voltage is passed through a temperature sensitive diode to create an analog signal. The analog signal is converted into digital temperature data by a A/D converter. The digital temperature data is then transmitted to a controlling host, without interfering with the normal operation of the device, by either transmitting the data in an out-of-band signal or during the clock refresh cycle. The controlling host, upon receipt of the temperature data, checks to see if the temperature level of the device has exceeded a threshold value.

    摘要翻译： 提出了一种用于使用直接嵌入设备中的温度感测电路对RAM器件的热感测和调节的方法和装置。 预定电压通过温度敏感二极管以产生模拟信号。 模拟信号由A / D转换器转换为数字温度数据。 然后，通过在带外信号中传输数据或在时钟刷新周期期间将数字温度数据发送到控制主机，而不干扰设备的正常操作。 控制主机在接收到温度数据后，检查设备的温度水平是否超过阈值。

    DYNAMIC LINKING OF CODESETS IN UNIVERSAL REMOTE CONTROL DEVICES
    10.
    发明申请
    DYNAMIC LINKING OF CODESETS IN UNIVERSAL REMOTE CONTROL DEVICES 有权
    通用远程控制设备中代码的动态链接

    公开(公告)号：US20110102230A1

    公开(公告)日：2011-05-05

    申请号：US13005017

    申请日：2011-01-12

    申请人： George Vergis ,  Sunilkumar Mankame

    发明人： George Vergis ,  Sunilkumar Mankame

    IPC分类号： H04L17/02

    CPC分类号： H04N5/4403 ,  G08C17/02 ,  G08C19/28 ,  G08C19/36 ,  G08C2201/20 ,  H04N21/42225

    摘要： A codeset having function-code combinations is provisioned on a controlling device to control functions of an intended target device. Input is provided to the controlling device which designates a function to be controlled on the intended target device. From a plurality of codes that are each associated with the designated function in a database stored in a memory of the controlling device a first code that is determined to be valid for use in controlling the designated function on the intended target device is selected. When the codeset is then provisioned on the controlling device, the provisioned codeset includes as a function-code combination thereof the designated function and the first code.

    摘要翻译： 具有功能代码组合的代码集被提供在控制设备上以控制预期目标设备的功能。 向控制装置提供输入，该控制装置指定要在目标装置上控制的功能。 从存储在控制装置的存储器中的数据库中的与指定功能相关联的多个代码中选择被确定为有效用于控制预期目标设备上的指定功能的第一代码。 当代码集然后在控制设备上被提供时，所提供的代码集包括作为其指定功能和第一代码的功能代码组合。