公开(公告)号：US20160284642A1

公开(公告)日：2016-09-29

申请号：US15037276

申请日：2013-12-23

Applicant: Sanka GANESAN ,  John S. GUZEK ,  Nitesh NIMKAR ,  Klaus REINGRUBER ,  Thorsten MEYER

Inventor： Sanka GANESAN ,  John S. GUZEK ,  Nitesh NIMKAR ,  Klaus REINGRUBER ,  Thorsten MEYER

IPC: H01L23/522 ,  H01L23/31 ,  H01L21/768 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L25/10

CPC classification number: H01L23/5226 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76877 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed to package assemblies and methods for fabricating package assemblies. In one embodiment, a package assembly includes a die at least partially embedded in a mold compound; and a through mold via (TMV). The TMV may have vertical sides or may include two different portions with varying shapes. In some instances, prefabricated via bars may be used during fabrication. Package assemblies of the present disclosure may include package-on-package (POP) interconnects having a pitch of less than 0.3 mm. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及用于制造包装组件的包装组件和方法。 在一个实施例中，包装组件包括至少部分地嵌入模具化合物中的模具; 和通孔（TMV）。 TMV可以具有垂直侧面或者可以包括具有变化形状的两个不同部分。 在一些情况下，可以在制造期间使用预制通孔条。 本公开的封装组件可以包括具有小于0.3mm的间距的封装封装（POP）互连。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20130335939A1

公开(公告)日：2013-12-19

申请号：US13992791

申请日：2011-12-06

Applicant: Aleksandar Aleksov ,  Sanka Ganesan

Inventor： Aleksandar Aleksov ,  Sanka Ganesan

IPC: B81B7/00

CPC classification number: B81B7/0006 ,  B23K35/0288 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/1132 ,  H01L2224/11474 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14177 ,  H01L2224/14179 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/01322 ,  H01L2924/3511 ,  H05K3/3436 ,  H05K2201/09418 ,  H05K2201/10734 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00

Abstract: The present description relates to the field of fabricating microelectronic assemblies, wherein a microelectronic device may be attached to a microelectronic substrate with a plurality of shaped and oriented solder joints. The shaped and oriented solder joints may be substantially oval, wherein the major axis of the substantially oval solder joints may be substantially oriented toward a neutral point or center of the microelectronic device. Embodiments of the shaped and oriented solder joint may reduce the potential of solder joint failure due to stresses, such as from thermal expansion stresses between the microelectronic device and the microelectronic substrate.

Abstract translation: 本说明书涉及制造微电子组件的领域，其中微电子器件可以附接到具有多个成形和取向的焊点的微电子衬底。 成形和定向的焊接接头可以是基本上椭圆形的，其中基本上椭圆形焊点的长轴可以基本上朝向微电子器件的中性点或中心定向。 成形和取向的焊接接头的实施例可以减少由于应力（例如来自微电子器件和微电子衬底之间的热膨胀应力）引起的焊点故障的可能性。

公开(公告)号：US08353101B2

公开(公告)日：2013-01-15

申请号：US13008849

申请日：2011-01-18

Applicant: Charan Gurumurthy ,  Sanka Ganesan ,  Chandrashekar Ramaswamy ,  Mark Hlad

Inventor： Charan Gurumurthy ,  Sanka Ganesan ,  Chandrashekar Ramaswamy ,  Mark Hlad

IPC: H05K3/00 ,  H01L21/46

CPC classification number: H01L23/48 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K1/113 ,  H05K3/00 ,  H05K3/108 ,  H05K3/222 ,  H05K3/426 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/10189 ,  H05K2201/10356 ,  H05K2201/1053 ,  H05K2201/10734 ,  H05K2203/167 ,  Y10T29/49124 ,  H01L2224/0401

Abstract: An assembly of substrate packages interconnected with flex cables and a method of fabrication of the substrate package. The assembly allows input/output (I/O) signals to be speedily transmitted between substrate packages via flex cable and without being routed through the motherboard. Embodiments relate to a substrate package providing separable inter-package flex cable connection. Hermetically-sealed guiding through holes are provided on the substrate package as a mechanical alignment feature to guide connection between flex cables and high speed I/O contact pads on the substrate package. Embodiments of the method of fabrication relate to simultaneously forming hermetically-sealed guiding through holes and I/O contact pads.

Abstract translation: 与柔性电缆互连的衬底封装的组件和衬底封装的制造方法。 该组件允许通过柔性电缆快速地在衬底封装之间传输输入/输出（I / O）信号，而不通过主板。 实施例涉及提供可分离的包装间柔性电缆连接的衬底封装。 在基板封装上提供密封导向孔，作为机械对准特征，以引导柔性电缆与基板封装上的高速I / O接触焊盘之间的连接。 制造方法的实施例涉及同时形成密封的引导通孔和I / O接触垫。

公开(公告)号：US09368437B2

公开(公告)日：2016-06-14

申请号：US13977658

申请日：2011-12-31

Applicant: Sanka Ganesan ,  Zhiguo Qian ,  Robert L. Sankman ,  Krishna Srinivasan ,  Zhaohui Zhu

Inventor： Sanka Ganesan ,  Zhiguo Qian ,  Robert L. Sankman ,  Krishna Srinivasan ,  Zhaohui Zhu

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/768 ,  H01L23/50 ,  H01L23/538

CPC classification number: H01L23/49811 ,  H01L21/76885 ,  H01L23/50 ,  H01L23/5386 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/1301 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13687 ,  H01L2224/14132 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16058 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/81411 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2924/05042 ,  H01L2924/1434 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.

Abstract translation: 描述了包括形成互连结构的电子组件和方法。 在一个实施例中，一种装置包括半导体管芯和裸片上的第一金属凸块，第一金属凸块包括具有第一部分和第二部分的表面。 该设备还包括覆盖表面的第一部分并且使表面的第二部分未被覆盖的耐焊接涂层。 描述和要求保护其他实施例。

公开(公告)号：US08508947B2

公开(公告)日：2013-08-13

申请号：US12896579

申请日：2010-10-01

Applicant: Sanka Ganesan ,  Mohiuddin Mazumder ,  Zhichao Zhang ,  Kemal Aygun

Inventor： Sanka Ganesan ,  Mohiuddin Mazumder ,  Zhichao Zhang ,  Kemal Aygun

IPC: H05K1/00 ,  H05K7/00

CPC classification number: H05K7/00 ,  H05K1/181 ,  H05K3/28 ,  H05K3/282 ,  H05K3/361 ,  H05K2201/10356 ,  H05K2201/1053 ,  H05K2201/10734 ,  H05K2203/167 ,  Y02P70/611

Abstract: An assembly of substrate packages interconnected with flex cables. The assembly allows input/output (I/O) signals to be speedily transmitted between substrate packages via flex cable and without being routed through the motherboard. Embodiments relate to a substrate package providing detachable inter-package flex cable connection. The flex cable comprises a transmission region that includes a plurality of signal traces and a ground plane. A plurality of solder mask strips are disposed on the plurality of signals traces to provide anchoring for the signal traces. The solder mask strips intersect the signals traces. The exposed signal traces and the ground plane are coated with organic solderability preservative material. Hermetically-sealed guiding through holes are provided on the substrate package as a mechanical alignment feature to guide connection between flex cables and high speed I/O contact pads on the substrate package. Embodiments of the method of fabrication relate to simultaneously forming hermetically-sealed guiding through holes and I/O contact pads.

Abstract translation: 与柔性电缆互连的衬底封装的组件。 该组件允许通过柔性电缆快速地在衬底封装之间传输输入/输出（I / O）信号，而不通过主板。 实施例涉及提供可拆卸的包装间柔性电缆连接的基板封装。 柔性电缆包括包括多个信号迹线和接地平面的透射区域。 多个焊接掩模条设置在多个信号迹线上以提供信号迹线的锚定。 焊接掩模条与信号迹线相交。 暴露的信号迹线和接地平面涂有有机可焊性防腐材料。 在基板封装上提供密封导向孔，作为机械对准特征，以引导柔性电缆与基板封装上的高速I / O接触焊盘之间的连接。 制造方法的实施例涉及同时形成密封的引导通孔和I / O接触垫。

公开(公告)号：US20110108427A1

公开(公告)日：2011-05-12

申请号：US13008849

申请日：2011-01-18

Applicant: Charan Gurumurthy ,  Sanka Ganesan ,  Chandrashekar Ramaswamy ,  Mark Hlad

Inventor： Charan Gurumurthy ,  Sanka Ganesan ,  Chandrashekar Ramaswamy ,  Mark Hlad

IPC: C25D5/02

CPC classification number: H01L23/48 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K1/113 ,  H05K3/00 ,  H05K3/108 ,  H05K3/222 ,  H05K3/426 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/10189 ,  H05K2201/10356 ,  H05K2201/1053 ,  H05K2201/10734 ,  H05K2203/167 ,  Y10T29/49124 ,  H01L2224/0401

Abstract: An assembly of substrate packages interconnected with flex cables and a method of fabrication of the substrate package. The assembly allows input/output (I/O) signals to be speedily transmitted between substrate packages via flex cable and without being routed through the motherboard. Embodiments relate to a substrate package providing separable inter-package flex cable connection. Hermetically-sealed guiding through holes are provided on the substrate package as a mechanical alignment feature to guide connection between flex cables and high speed I/O contact pads on the substrate package. Embodiments of the method of fabrication relate to simultaneously forming hermetically-sealed guiding through holes and I/O contact pads.

Abstract translation: 与柔性电缆互连的衬底封装的组件和衬底封装的制造方法。 该组件允许通过柔性电缆快速地在衬底封装之间传输输入/输出（I / O）信号，而不通过主板。 实施例涉及提供可分离的包装间柔性电缆连接的衬底封装。 在基板封装上提供密封导向孔，作为机械对准特征，以引导柔性电缆与基板封装上的高速I / O接触焊盘之间的连接。 制造方法的实施例涉及同时形成密封的引导通孔和I / O接触垫。

公开(公告)号：US10903166B2

公开(公告)日：2021-01-26

申请号：US16060918

申请日：2016-01-28

Applicant: Sanka Ganesan ,  Thorsten Meyer ,  Gerald Ofner ,  Intel IP Corporation

Inventor： Sanka Ganesan ,  Thorsten Meyer ,  Gerald Ofner

IPC: H01L29/40 ,  H01L23/532 ,  H01L21/66 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

Abstract: Disclosed herein are integrated circuit (IC) packages, and related structures and techniques. In some embodiments, an IC package may include: a die; a redistribution structure, wherein the die is coupled to the redistribution structure via first-level interconnects and solder; a solder resist; and second-level interconnects coupled to the redistribution structure through openings in the solder resist.

公开(公告)号：US20140273552A1

公开(公告)日：2014-09-18

申请号：US13844501

申请日：2013-03-15

Applicant: Sanka GANESAN ,  Timothy M. SWETTLEN ,  Gary B. LONG ,  Donald T. TRAN ,  Jill D. MURFIN ,  David D. AMIR

Inventor： Sanka GANESAN ,  Timothy M. SWETTLEN ,  Gary B. LONG ,  Donald T. TRAN ,  Jill D. MURFIN ,  David D. AMIR

IPC: H05K1/14

CPC classification number: H01R43/0249 ,  H01R43/205 ,  H01R2107/00 ,  H01R2201/04 ,  H05K1/144 ,  H05K1/147 ,  H05K3/363 ,  H05K2201/042 ,  H05K2201/056 ,  H05K2201/10189 ,  H05K2201/1053 ,  H05K2201/2009

Abstract: Stacked flex cable assemblies and their manufacture are described. One assembly includes a first flex cable and a second flex cable electrically coupled to the first flex cable. The assembly also includes a connector electrically coupled to the first flex cable. The first flex cable is positioned between the connector and the second flex cable. Other embodiments are described and claimed.

Abstract translation: 描述了堆叠的柔性电缆组件及其制造。 一个组件包括电耦合到第一柔性电缆的第一柔性电缆和第二柔性电缆。 组件还包括电连接到第一柔性电缆的连接器。 第一柔性电缆位于连接器和第二柔性电缆之间。 描述和要求保护其他实施例。

公开(公告)号：US20140217579A1

公开(公告)日：2014-08-07

申请号：US13977658

申请日：2011-12-31

Applicant: Sanka Ganesan ,  Zhiguo Qian ,  Robert L. Sankman ,  Krishna Srinivasan ,  Zhaohui Zhu

Inventor： Sanka Ganesan ,  Zhiguo Qian ,  Robert L. Sankman ,  Krishna Srinivasan ,  Zhaohui Zhu

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/49811 ,  H01L21/76885 ,  H01L23/50 ,  H01L23/5386 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/1301 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13687 ,  H01L2224/14132 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16058 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/81411 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2924/05042 ,  H01L2924/1434 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.

Abstract translation: 描述了包括形成互连结构的电子组件和方法。 在一个实施例中，一种装置包括半导体管芯和裸片上的第一金属凸块，第一金属凸块包括具有第一部分和第二部分的表面。 该设备还包括覆盖表面的第一部分并且使表面的第二部分未被覆盖的耐焊接涂层。 描述和要求保护其他实施例。

公开(公告)号：US08188594B2

公开(公告)日：2012-05-29

申请号：US12587175

申请日：2009-10-01

Applicant: Sanka Ganesan ,  Kemal Aygun ,  Chandrashekhar Ramaswamy ,  Eric Palmer ,  Henning Braunisch

Inventor： Sanka Ganesan ,  Kemal Aygun ,  Chandrashekhar Ramaswamy ,  Eric Palmer ,  Henning Braunisch

IPC: H01L23/34 ,  H01L23/10 ,  H01L23/28 ,  H01L23/495 ,  H01L23/48 ,  H01L23/52 ,  H01L23/04

CPC classification number: H01L23/34 ,  H01L23/367 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/50 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/19032 ,  H01L2224/0401

Abstract: A high-speed I/O trace is part of an I/O package architecture for an integrated circuit package substrate. The integrated circuit package substrate includes an integrated heat spreader footprint on a die-side and the I/O trace to couple with an IC device to be disposed inside the IHS footprint. The I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint. The high-speed I/O trace can sustain a data flow rate from a processor in a range from 5 gigabits per second (Gb/s) to 40 Gb/s.

Abstract translation: 高速I / O迹线是集成电路封装基板的I / O封装架构的一部分。 集成电路封装衬底包括在芯片侧的集成的散热器占地面积，并且I / O迹线与要设置在IHS占地面积内的IC器件耦合。 I / O跟踪包括IHS封装之外的引脚输出端子，以连接到要设置在IHS占用空间之外的IC器件。 高速I / O跟踪可以维持从5吉比特每秒（Gb / s）到40 Gb / s的处理器的数据流速。