利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

268 条记录 (耗时 0.028 秒)

    Protective hardmask for producing interconnect structures
    1.
    发明授权
    Protective hardmask for producing interconnect structures 失效
    用于生产互连结构的保护硬掩模

    公开(公告)号：US06720249B1

    公开(公告)日：2004-04-13

    申请号：US09550943

    申请日：2000-04-17

    申请人： Timothy J. Dalton ,  Christopher V. Jahnes ,  Joyce C. Liu ,  Sampath Purushothaman

    发明人： Timothy J. Dalton ,  Christopher V. Jahnes ,  Joyce C. Liu ,  Sampath Purushothaman

    IPC分类号： H01L214763

    CPC分类号： H01L21/76835 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention provides a permanent protective hardmask which protects the dielectric properties of a main dielectric layer having a desirably low dielectric constant in a semiconductor device from undesirable increases in the dielectric constant, undesirable increases in current leakage, and low device yield from surface scratching during subsequent processing steps. The protective hardmask further includes a single layer or dual layer sacrificial hardmask particularly useful when interconnect structures such as via openings and/or lines are formed in the low dielectric material during the course of making the final product. The sacrificial hardmask layers and the permanent hardmask layer may be formed in a single step from a same precursor wherein process conditions are altered to provide films of differing dielectric constants. Most preferably, a dual damascene structure has a tri-layer hardmask comprising silicon carbide BLoK™, PECVD silicon nitride, and PECVD silicon dioxide, respectively, formed over a bulk low dielectric constant interlevel dielectric prior to forming the interconnect structures in the interlevel dielectric.

    摘要翻译： 本发明提供一种永久性保护性硬掩模，其保护半导体器件中具有期望的低介电常数的主电介质层的介电性能，不需要介电常数的增加，不期望的电流泄漏增加，以及在表面划伤期间的低的器件产量 后续处理步骤。 保护性硬掩模还包括单层或双层牺牲硬掩模，在制造最终产品的过程中，在低电介质材料中形成诸如通孔开口和/或线之间的互连结构时尤其有用。 牺牲硬掩模层和永久硬掩模层可以从相同的前体在单个步骤中形成，其中改变工艺条件以提供不同介电常数的膜。 最优选地，双镶嵌结构具有三层硬掩模，其在形成层间的互连结构之前分别形成在体低介电常数层间电介质上的碳化硅BLoK TM，PECVD氮化硅和PECVD二氧化硅 电介质。

    Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same
    3.
    发明授权
    Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same 失效
    具有低介电常数绝缘体的芯片互连布线结构及其制造方法

    公开(公告)号：US06184121B2

    公开(公告)日：2001-02-06

    申请号：US09112919

    申请日：1998-07-09

    申请人： Leena P. Buchwalter ,  Alessandro Cesare Callegari ,  Stephan Alan Cohen ,  Teresita Ordonez Graham ,  John P. Hummel ,  Christopher V. Jahnes ,  Sampath Purushothaman ,  Katherine Lynn Saenger ,  Jane Margaret Shaw

    发明人： Leena P. Buchwalter ,  Alessandro Cesare Callegari ,  Stephan Alan Cohen ,  Teresita Ordonez Graham ,  John P. Hummel ,  Christopher V. Jahnes ,  Sampath Purushothaman ,  Katherine Lynn Saenger ,  Jane Margaret Shaw

    IPC分类号： H01L214763

    CPC分类号： H01L23/53228 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method to achieve a very low effective dielectric constant in high performance back end of the line chip interconnect wiring and the resulting multilayer structure are disclosed. The process involves fabricating the multilayer interconnect wiring structure by methods and materials currently known in the state of the art of semiconductor processing; removing the intralevel dielectric between the adjacent metal features by a suitable etching process; applying a thin passivation coating over the exposed etched structure; annealing the etched structure to remove plasma damage; laminating an insulating cover layer to the top surface of the passivated metal features; optionally depositing an insulating environmental barrier layer on top of the cover layer; etching vias in the environmental barrier layer, cover layer and the thin passivation layer for terminal pad contacts; and completing the device by fabricating terminal input/output pads. The method obviates issues such as processability and thermal stability associated with low dielectric constant materials by avoiding their use. Since air, which has the lowest dielectric constant, is used as the intralevel dielectric the structure created by this method would possess a very low capacitance and hence fast propagation speeds. Such structure is ideally suitable for high density interconnects required in high performance microelectronic device chips.

    摘要翻译： 公开了一种在线芯片互连布线和所得多层结构的高性能后端中实现非常低的有效介电常数的方法。 该方法涉及通过目前在半导体处理领域中已知的方法和材料制造多层互连布线结构; 通过合适的蚀刻工艺去除相邻金属特征之间的层间电介质; 在暴露的蚀刻结构上施加薄的钝化涂层; 退火蚀刻结构以去除等离子体损伤; 将绝缘覆盖层层压到钝化金属特征的顶表面; 可选地在覆盖层的顶部上沉积绝缘环境阻挡层; 在环境阻挡层，覆盖层和用于端子焊盘触点的薄钝化层中蚀刻通孔; 并通过制造端子输入/输出焊盘来完成该器件。 该方法通过避免其使用而消除了与低介电常数材料相关的加工性和热稳定性等问题。 由于具有最低介电常数的空气被用作体内电介质，所以通过该方法产生的结构将具有非常低的电容并因此具有快速的传播速度。 这种结构理想地适用于高性能微电子器件芯片所需的高密度互连。