公开(公告)号：US20160181511A1

公开(公告)日：2016-06-23

申请号：US15057101

申请日：2016-02-29

Applicant: HYUNGJOON KWON ,  SECHUNG OH ,  VLADIMIR URAZAEV ,  KEN TOKASHIKI ,  JONGCHUL PARK ,  Gwang-Hyun BAEK ,  Jaehun SEO ,  SANGMIN LEE

Inventor： HYUNGJOON KWON ,  SECHUNG OH ,  VLADIMIR URAZAEV ,  KEN TOKASHIKI ,  JONGCHUL PARK ,  Gwang-Hyun BAEK ,  Jaehun SEO ,  SANGMIN LEE

IPC: H01L43/02 ,  H01L27/22

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L27/222 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2463 ,  H01L43/02 ,  H01L43/10 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148

Abstract: Provided are semiconductor devices and methods of fabricating the same. The semiconductor device may include lower wires, upper wires crossing the lower wires, select elements provided at intersections between the lower and upper wires, and memory elements provided between the select elements and the upper wires. Each of the memory elements may include a lower electrode having a top width greater than a bottom width, and a data storage layer including a plurality of magnetic layers stacked on a top surface of the lower electrode and having a rounded edge.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件可以包括下部布线，穿过下部布线的上部布线，在下部布线和上部布线之间的交叉处提供的选择元件以及设置在选择元件和上部布线之间的存储元件。 每个存储元件可以包括具有大于底部宽度的顶部宽度的下部电极，以及包括堆叠在下部电极的顶表面上并且具有圆形边缘的多个磁性层的数据存储层。

公开(公告)号：US20110143537A1

公开(公告)日：2011-06-16

申请号：US12913965

申请日：2010-10-28

Applicant: Jeong-Yun LEE ,  Ken TOKASHIKI ,  Kyoung-Sub SHIN ,  Jun-Ho YOON ,  Hong CHO

Inventor： Jeong-Yun LEE ,  Ken TOKASHIKI ,  Kyoung-Sub SHIN ,  Jun-Ho YOON ,  Hong CHO

IPC: H01L21/768

CPC classification number: H01J37/32165 ,  H01J37/32082 ,  H01J37/32155

Abstract: Provided are a method of fabricating a semiconductor device and synchronous pulse plasma etching equipment for the same. The method includes outputting a first radio frequency (RF) power and a control signal and outputting a second RF power. The first RF power is pulse-width modulated to have a first frequency and a first duty ratio, and is applied to a first electrode in a plasma etching chamber. The control signal includes information on a phase of the first RF power. The second RF power is pulse-width modulated to have the first frequency and a second duty ratio smaller than the first duty ratio, is applied to a corresponding second electrode among second electrodes in the plasma etching chamber, and is supplied for a time section in which the first RF power is supplied.

Abstract translation: 提供一种半导体器件和同步脉冲等离子体蚀刻设备的制造方法。 该方法包括输出第一射频（RF）功率和控制信号并输出​​第二RF功率。 第一RF功率被脉冲宽度调制以具有第一频率和第一占空比，并且被施加到等离子体蚀刻室中的第一电极。 控制信号包括关于第一RF功率的相位的信息。 第二RF功率被脉冲宽度调制成具有小于第一占空比的第一频率和第二占空比，被施加到等离子体蚀刻室中的第二电极中的对应的第二电极，并且被提供给 提供第一RF功率。

公开(公告)号：US20160064194A1

公开(公告)日：2016-03-03

申请号：US14844057

申请日：2015-09-03

Applicant: KEN TOKASHIKI ,  Sungil CHO ,  Kyungho JANG

Inventor： KEN TOKASHIKI ,  Sungil CHO ,  Kyungho JANG

IPC: H01J37/32 ,  H01L21/683 ,  H01L21/67

CPC classification number: H01J37/32165 ,  H01J37/32091 ,  H01J37/32174 ,  H01J37/32577 ,  H01L21/6831

Abstract: The disclosure provides a semiconductor fabricating apparatus and a method of fabricating a semiconductor device using the same. In some embodiments, the apparatus may synchronize low-frequency, high-frequency and direct current (DC) powers that are applied to an electrode. The low-frequency power may have a non-sinusoidal waveform. Thus, reliability and reproducibility of a semiconductor fabrication process may be improved. In other embodiments, the apparatus may include a first low-frequency power generator generating a first low-frequency power having a sinusoidal waveform and a second low-frequency power generator generating a second low-frequency power having a non-sinusoidal waveform.

Abstract translation: 本发明提供半导体制造装置和使用其制造半导体器件的方法。 在一些实施例中，该装置可以同步施加到电极的低频，高频和直流（DC）功率。 低频功率可能具有非正弦波形。 因此，可以提高半导体制造工艺的可靠性和再现性。 在其他实施例中，该装置可以包括产生具有正弦波形的第一低频功率的第一低频功率发生器和产生具有非正弦波形的第二低频功率的第二低频功率发生器。

公开(公告)号：US09246082B2

公开(公告)日：2016-01-26

申请号：US14286407

申请日：2014-05-23

Applicant: Ken Tokashiki

Inventor： Ken Tokashiki

IPC: H01L21/00 ,  H01L43/12 ,  H01L21/02 ,  H01L27/22

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L21/02071 ,  H01L27/222 ,  H01L27/224 ,  H01L27/226

Abstract: Provided is a method of forming a magnetic memory device. A first magnetic layer, a tunnel barrier, and a second magnetic layer are deposited on a substrate. The second magnetic layer, the tunnel barrier, and the first magnetic layer are etched to form magnetic tunnel junction structures. An ion beam etching process is performed using an oxygen-containing source gas to remove etching by-products on sidewalls of the magnetic tunnel junction structure and to oxidize the sidewalls of the magnetic tunnel junction structures.

Abstract translation: 提供一种形成磁存储器件的方法。 在基板上沉积第一磁性层，隧道势垒和第二磁性层。 蚀刻第二磁性层，隧道势垒和第一磁性层以形成磁性隧道结结构。 使用含氧源气体进行离子束蚀刻工艺，以去除在磁性隧道结结构的侧壁上的蚀刻副产物并氧化磁性隧道结结构的侧壁。

公开(公告)号：US20150069560A1

公开(公告)日：2015-03-12

申请号：US14311238

申请日：2014-06-20

Applicant: Yoonchul CHO ,  Ken TOKASHIKI

Inventor： Yoonchul CHO ,  Ken TOKASHIKI

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

CPC classification number: H01L43/02 ,  G11C11/161 ,  H01L27/226 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

Abstract: Magnetic memory devices and methods of manufacturing the same are disclosed. A method may include forming a magnetic tunnel junction layer on a substrate, forming mask patterns on the magnetic tunnel junction layer, and sequentially performing a plurality of ion implantation processes using the mask patterns as ion implantation masks to form an isolation region in the magnetic tunnel junction layer. The isolation region may thereby define magnetic tunnel junction parts that are disposed under corresponding ones of the mask patterns. A magnetic memory device may include a plurality of magnetic tunnel junction parts electrically and magnetically isolated from each other through the isolation region.

Abstract translation: 公开了磁存储器件及其制造方法。 一种方法可以包括在衬底上形成磁性隧道结层，在磁性隧道结层上形成掩模图案，并使用掩模图案依次执行多个离子注入工艺，作为离子注入掩模，以在磁隧道中形成隔离区 结层。 因此，隔离区域可以限定设置在相应的掩模图案下的磁性隧道结部分。 磁存储器件可以包括通过隔离区域彼此电隔离和磁隔离的多个磁性隧道结部分。

公开(公告)号：US20150044781A1

公开(公告)日：2015-02-12

申请号：US14286407

申请日：2014-05-23

Applicant: Ken TOKASHIKI

Inventor： Ken TOKASHIKI

IPC: H01L43/12

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L21/02071 ,  H01L27/222 ,  H01L27/224 ,  H01L27/226

Abstract: Provided is a method of forming a magnetic memory device. A first magnetic layer, a tunnel barrier, and a second magnetic layer are deposited on a substrate. The second magnetic layer, the tunnel barrier, and the first magnetic layer are etched to form magnetic tunnel junction structures. An ion beam etching process is performed using an oxygen-containing source gas to remove etching by-products on sidewalls of the magnetic tunnel junction structure and to oxidize the sidewalls of the magnetic tunnel junction structures.

Abstract translation: 提供一种形成磁存储器件的方法。 在基板上沉积第一磁性层，隧道势垒和第二磁性层。 蚀刻第二磁性层，隧道势垒和第一磁性层以形成磁性隧道结结构。 使用含氧源气体进行离子束蚀刻工艺，以去除在磁性隧道结结构的侧壁上的蚀刻副产物并氧化磁性隧道结结构的侧壁。

公开(公告)号：US07988874B2

公开(公告)日：2011-08-02

申请号：US12913965

申请日：2010-10-28

Applicant: Jeong-Yun Lee ,  Ken Tokashiki ,  Kyoung-Sub Shin ,  Jun-Ho Yoon ,  Hong Cho

Inventor： Jeong-Yun Lee ,  Ken Tokashiki ,  Kyoung-Sub Shin ,  Jun-Ho Yoon ,  Hong Cho

IPC: C03C15/00 ,  C03C25/68 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01J37/32165 ,  H01J37/32082 ,  H01J37/32155

Abstract: Provided are a method of fabricating a semiconductor device and synchronous pulse plasma etching equipment for the same. The method includes outputting a first radio frequency (RF) power and a control signal and outputting a second RF power. The first RF power is pulse-width modulated to have a first frequency and a first duty ratio, and is applied to a first electrode in a plasma etching chamber. The control signal includes information on a phase of the first RF power. The second RF power is pulse-width modulated to have the first frequency and a second duty ratio smaller than the first duty ratio, is applied to a corresponding second electrode among second electrodes in the plasma etching chamber, and is supplied for a time section in which the first RF power is supplied.

Abstract translation: 提供一种半导体器件和同步脉冲等离子体蚀刻设备的制造方法。 该方法包括输出第一射频（RF）功率和控制信号并输出​​第二RF功率。 第一RF功率被脉冲宽度调制以具有第一频率和第一占空比，并且被施加到等离子体蚀刻室中的第一电极。 控制信号包括关于第一RF功率的相位的信息。 第二RF功率被脉冲宽度调制成具有小于第一占空比的第一频率和第二占空比，被施加到等离子体蚀刻室中的第二电极中的对应的第二电极，并且被提供给 提供第一RF功率。

公开(公告)号：US20100130018A1

公开(公告)日：2010-05-27

申请号：US12591602

申请日：2009-11-24

Applicant: Ken Tokashiki ,  Hong Cho ,  Jeong-Dong Choe

Inventor： Ken Tokashiki ,  Hong Cho ,  Jeong-Dong Choe

IPC: H01L21/3065

CPC classification number: H01J37/32165 ,  H01J37/32082 ,  H01J37/32174

Abstract: Synchronous pulse plasma etching equipment includes a first electrode and one or more second electrodes configured to generate plasma in a plasma etching chamber. A first radio frequency power output unit is configured to apply a first radio frequency power having a first frequency and a first duty ratio to the first electrode, and to output a control signal including information about a phase of the first radio frequency power. At least one second radio frequency power output unit is configured to apply a second radio frequency power having a second frequency and a second duty ratio to a corresponding second electrode among the second electrodes. The second radio frequency power output unit is configured to control the second radio frequency power to be synchronized with the first radio frequency power or to have a phase difference from the first radio frequency power in response to the control signal.

Abstract translation: 同步脉冲等离子体蚀刻设备包括第一电极和被配置为在等离子体蚀刻室中产生等离子体的一个或多个第二电极。 第一射频功率输出单元被配置为向第一电极施加具有第一频率和第一占空比的第一射频功率，并且输出包括关于第一射频功率的相位的信息的控制信号。 至少一个第二射频功率输出单元被配置为将具有第二频率和第二占空比的第二射频功率应用于第二电极中的对应的第二电极。 第二射频功率输出单元被配置为响应于控制信号控制与第一射频功率同步的第二射频功率或者与第一射频功率相位差。

公开(公告)号：US06372654B1

公开(公告)日：2002-04-16

申请号：US09543734

申请日：2000-04-05

Applicant: Ken Tokashiki

Inventor： Ken Tokashiki

IPC: H01L213065

CPC classification number: H01L21/67069 ,  H01J37/321 ,  H01L21/32136

Abstract: There is provided a method of fabricating a semiconductor device, including the steps of (a) generating plasma in the following conditions: (a1) an RF bias voltage has a frequency equal to or greater than 1 MHz, (a2) an RF source voltage has a frequency equal to or greater than 1 MHz, (a3) the RF source voltage is modulated by pulses in a cycle equal to or greater than 100 &mgr;sec, and (a4) pulse-on time is equal to or greater than 50 &mgr;sec, and (b) patterning multi-layered metal wirings by etching through the plasma The method makes it possible to reduce charging damage to a gate insulating film, even if wirings are further spaced away from adjacent ones and/or an antenna ratio of multi-layered metal wirings is further increased.

Abstract translation: 提供了制造半导体器件的方法，包括以下步骤：（a）在以下条件下产生等离子体：（a1）RF偏置电压具有等于或大于1MHz的频率，（a2）RF源电压 具有等于​​或大于1MHz的频率，（a3）RF源电压由等于或大于100个音频的周期的脉冲调制，并且（a4）脉冲开启时间等于或大于50个音频， 和（b）通过等离子体蚀刻图案化多层金属配线。该方法可以减小对栅极绝缘膜的充电损伤，即使布线与相邻布线进一步间隔开，和/或多层天线的天线比 金属布线进一步增加。

公开(公告)号：US20150287911A1

公开(公告)日：2015-10-08

申请号：US14611717

申请日：2015-02-02

Applicant: Kyoung-Sun KIM ,  Woo-Jin KIM ,  Ken TOKASHIKI

Inventor： Kyoung-Sun KIM ,  Woo-Jin KIM ,  Ken TOKASHIKI

IPC: H01L43/12 ,  H01L27/22

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L27/228

Abstract: In a method of manufacturing a MRAM device, a lower electrode is formed on a substrate. A first magnetic layer, a tunnel barrier layer, and a second magnetic layer are sequentially formed on the lower electrode layer. An etching mask is formed on the second magnetic layer. An ion beam etching process in which a first ion beam and a second ion beam are simultaneously emitted onto the substrate is performed to form a MTJ structure including a first magnetic layer pattern, a tunnel layer pattern, and a second magnetic layer pattern from the first magnetic layer, the tunnel barrier layer, and the second magnetic layer, respectively, the MTJ structure has no by-products remaining after the ion beam etching process is performed.

Abstract translation: 在制造MRAM器件的方法中，在基片上形成下电极。 第一磁性层，隧道势垒层和第二磁性层依次形成在下部电极层上。 在第二磁性层上形成蚀刻掩模。 执行其中第一离子束和第二离子束同时发射到衬底上的离子束蚀刻工艺，以形成包括第一磁性层图案，隧道层图案和第二磁性层图案的MTJ结构 磁性层，隧道势垒层和第二磁性层，在执行离子束蚀刻处理之后，MTJ结构没有剩余副产物。