公开(公告)号：US06881639B2

公开(公告)日：2005-04-19

申请号：US10372774

申请日：2003-02-26

申请人： Kazuhiro Mochizuki ,  Kiyoshi Ouchi ,  Tomonori Tanoue

发明人： Kazuhiro Mochizuki ,  Kiyoshi Ouchi ,  Tomonori Tanoue

IPC分类号： H01L21/265 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8252 ,  H01L27/06 ,  H01L29/737 ,  H03F1/30 ,  H03F3/19

CPC分类号： H01L21/263 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/66318 ,  H01L29/7371 ,  H03F1/302 ,  H03F3/19

摘要： The present invention provides a method of manufacturing semiconductor devices, by which InGaAs-base C-top HBTs are manufactured at low cost. Helium ions with a smaller radius are implanted into a p-type InGaAs layer (in external base regions) not covered with a lamination consisting of an undoped InGaAs spacer layer, n-type InP collector layer, n-type InGaAs cap layer, and collector electrode from a direction vertical to the surface of the external base layer or within an angle of 3 degrees off the vertical. In consequence, the p-type InGaAs in the external base regions remains p-type conductive and low resistive and the n-type InAlAs layer in the external emitter regions can be made highly resistive. By this method, InGaAs-base C-top HBTs can be fabricated on a smaller chip at low cost without increase of the number of processes.

摘要翻译： 本发明提供一种半导体器件的制造方法，以低成本制造InGaAs基C顶HBT。 具有较小半径的氦离子注入未被不掺杂的InGaAs间隔层，n型InP集电极层，n型InGaAs覆盖层和集电体组成的叠层的p型InGaAs层（在外部基极区域中） 电极从垂直于外部基底层的表面的方向延伸，或者垂直于3度的角度。 因此，外部基极区域中的p型InGaAs保持p型导电和低电阻，并且外部发射极区域中的n型InAlAs层可以被制成高电阻性。 通过这种方法，可以以较低的成本在较小的芯片上制造InGaAs基C顶HBT，而不增加工艺数量。

公开(公告)号：US20060081879A1

公开(公告)日：2006-04-20

申请号：US11247234

申请日：2005-10-12

申请人： Kenichi Tanaka ,  Hidetoshi Matsumoto ,  Isao Ohbu ,  Kazuhiro Mochizuki ,  Tomonori Tanoue ,  Chisaki Takubo ,  Hiroyuki Uchiyama

发明人： Kenichi Tanaka ,  Hidetoshi Matsumoto ,  Isao Ohbu ,  Kazuhiro Mochizuki ,  Tomonori Tanoue ,  Chisaki Takubo ,  Hiroyuki Uchiyama

IPC分类号： H01L31/109

CPC分类号： H01L23/482 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention provides a semiconductor device which comprises active components, passive components, wiring lines and electrodes and are satisfactory in terms of mechanical strength, miniaturization and thermal stability. In the semiconductor device, openings are formed just below active components. These openings are filled with conductor layers. Conductor layers are also formed where openings are not formed.

摘要翻译： 本发明提供一种半导体器件，其包括有源部件，无源部件，布线和电极，并且在机械强度，小型化和热稳定性方面令人满意。 在半导体器件中，开口形成在活性部件的正下方。 这些开口填充有导体层。 还形成了未形成开口的导体层。

公开(公告)号：US06943387B2

公开(公告)日：2005-09-13

申请号：US10409455

申请日：2003-04-09

申请人： Isao Ohbu ,  Tomonori Tanoue ,  Chushiro Kusano ,  Yasunari Umemoto ,  Atsushi Kurokawa ,  Kazuhiro Mochizuki ,  Masami Ohnishi ,  Hidetoshi Matsumoto

发明人： Isao Ohbu ,  Tomonori Tanoue ,  Chushiro Kusano ,  Yasunari Umemoto ,  Atsushi Kurokawa ,  Kazuhiro Mochizuki ,  Masami Ohnishi ,  Hidetoshi Matsumoto

IPC分类号： H01L21/331 ,  H01L29/06 ,  H01L29/423 ,  H01L29/737 ,  H03F1/30 ,  H03F3/19 ,  H01L31/072

CPC分类号： H01L29/66318 ,  H01L29/0692 ,  H01L29/42304 ,  H01L29/7371 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/16152 ,  H03F1/302 ,  H03F3/19 ,  H03F2203/21178

摘要： In a semiconductor device using an emitter top heterojunction bipolar transistor having a planar shape in a ring-like shape, a structure is provided in which a base electrode is present only on an inner side of a ring-like emitter-base junction region. This allows reduction of base/collector junction capacitance per unit emitter area, whereby a semiconductor device having high power adding efficiency and high power gain suitable for a power amplifier can be realized. Further, in a multistage power amplifier including first and second amplifier circuits each having one or more of bipolar transistors, a bipolar transistor in the first amplifier circuit uses an emitter having a planar shape in a rectangular shape, and a bipolar transistor in the second amplifier circuit uses an emitter having a ring-like shape and a base electrode only on the inner side of the emitter.

摘要翻译： 在使用具有环状形状的发射极顶面异质结双极晶体管的半导体器件中，提供了仅在环状发射极 - 基极结区域的内侧存在基极的结构。 这允许减小每单位发射极面积的基极/集电极结电容，由此可以实现具有高功率增加效率和适用于功率放大器的高功率增益的半导体器件。 此外，在包括具有一个或多个双极晶体管的第一和第二放大器电路的多级功率放大器中，第一放大器电路中的双极晶体管使用具有矩形形状的平面形状的发射极和第二放大器中的双极晶体管 电路仅在发射体的内侧使用具有环状形状的发射体和基极。

公开(公告)号：US20060138458A1

公开(公告)日：2006-06-29

申请号：US11316908

申请日：2005-12-27

申请人： Kenichi Tanaka ,  Tomonori Tanoue ,  Hidetoshi Matsumoto ,  Hiroshi Ohta ,  Kazuhiro Mochizuki ,  Hiroyuki Uchiyama

发明人： Kenichi Tanaka ,  Tomonori Tanoue ,  Hidetoshi Matsumoto ,  Hiroshi Ohta ,  Kazuhiro Mochizuki ,  Hiroyuki Uchiyama

IPC分类号： H01L31/109

CPC分类号： H01L29/7371 ,  H01L29/66318

摘要： This invention is intended to provide an HBT capable of achieving, if the HBT is a collector-up HBT, the constriction of the emitter layer disposed directly under an external base layer, and reduction in base-emitter junction capacity, or if the HBT is an emitter-up HBT, reduction in base-collector junction capacity. For the collector-up HBT, window structures around the sidewalls of a collector are used to etch either the emitter layer disposed directly under the external base layer, or an emitter contact layer For the emitter-up HBT, window structures around the sidewalls of an emitter are used to etch either the collector layer disposed directly under the external base layer, or a collector contact layer. In both HBTs, the external base layer is supported by a columnar structure to ensure mechanical strength.

摘要翻译： 本发明旨在提供一种如果HBT是集电极HBT，则可以实现直接位于外部基极层下方的发射极层的收缩，以及基极 - 发射极结能量的降低，或HBT为 发射极HBT，基极 - 集电极结电容降低。 对于收集器HBT，围绕集电极侧壁的窗口结构用于蚀刻直接位于外部基极层下方的发射极层或发射极接触层。对于发射极上升HBT，围绕侧壁的窗口结构 发射极用于蚀刻直接位于外部基底层下方的集电极层或集电极接触层。 在两个HBT中，外部基层由柱状结构支撑以确保机械强度。

公开(公告)号：US20050040497A1

公开(公告)日：2005-02-24

申请号：US10878358

申请日：2004-06-29

申请人： Chisaki Takubo ,  Hiroji Yamada ,  Kazuhiro Mochizuki ,  Kenichi Tanaka ,  Tomonori Tanoue ,  Hiroyuki Uchiyama

发明人： Chisaki Takubo ,  Hiroji Yamada ,  Kazuhiro Mochizuki ,  Kenichi Tanaka ,  Tomonori Tanoue ,  Hiroyuki Uchiyama

IPC分类号： H01L21/331 ,  H01L21/306 ,  H01L29/04 ,  H01L29/06 ,  H01L29/737

CPC分类号： H01L29/7371 ,  H01L21/30612 ,  H01L29/045 ,  H01L29/0657

摘要： The technical subject of the invention is to inhibit disconnection of electrodes caused by a step and bursting caused by residual air. That is, an object of the present invention is to provide a semiconductor device capable of overcoming a drawback due to the shape of a concave portion present in the zinc blende type compound semiconductor substrate in which the area of the bottom is larger than the surface in the cross sectional shape, as well as a manufacturing method thereof. According to the invention, a hole or step present in the semiconductor substrate constituting the semiconductor device is formed into a normal mesa shape irrespective of the orientation of the crystals on the surface of the semiconductor substrate. Accordingly, the present invention uses a novel wet etching solution having an etching rate for a portion below the etching mask higher than that in the direction of the depth of the semiconductor substrate.

摘要翻译： 本发明的技术课题是抑制由残留空气引起的台阶和破裂引起的电极断开。 也就是说，本发明的目的是提供一种半导体器件，其能够克服存在于闪锌矿型化合物半导体衬底中的凹部的形状的缺陷，其中底部的面积大于其中的表面 横截面形状及其制造方法。 根据本发明，构成半导体器件的半导体衬底中存在的孔或台阶形成为正常的台面形状，而与半导体衬底的表面上的晶体取向无关。 因此，本发明使用对蚀刻掩模下方的蚀刻速度高于半导体衬底的深度方向的蚀刻速率的新型湿式蚀刻溶液。

公开(公告)号：US20070073448A1

公开(公告)日：2007-03-29

申请号：US11583885

申请日：2006-10-20

申请人： Chisaki Takubo ,  Hiroji Yamada ,  Kazuhiro Mochizuki ,  Kenichi Tanaka ,  Tomonori Tanoue ,  Hiroyuki Uchiyama

发明人： Chisaki Takubo ,  Hiroji Yamada ,  Kazuhiro Mochizuki ,  Kenichi Tanaka ,  Tomonori Tanoue ,  Hiroyuki Uchiyama

IPC分类号： G05D1/10

CPC分类号： H01L21/30617 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/66318 ,  H01L29/7371

摘要： A semiconductor device capable of overcoming a drawback due to the shape of a concave portion present in the zinc blende type compound semiconductor substrate in which the area of the bottom is larger than the surface in the cross sectional shape, as well as a manufacturing method thereof. A hole or step present in the semiconductor substrate constituting the semiconductor device is formed into a normal mesa shape irrespective of the orientation of the crystals on the surface of the semiconductor substrate. A wet etching solution having an etching rate for a portion below the etching mask higher than that in the direction of the depth of the semiconductor substrate is used.

摘要翻译： 一种半导体器件及其制造方法，其能够克服存在于闪锌矿型化合物半导体衬底中的凹部的形状的缺陷，其中底部的面积大于截面形状的表面，以及其制造方法 。 存在于构成半导体器件的半导体衬底中的孔或台阶形成为正常台面形状，而与半导体衬底的表面上的晶体取向无关。 使用对蚀刻掩模下方的蚀刻速率比半导体衬底的深度方向的蚀刻速度更高的湿蚀刻溶液。

公开(公告)号：US20060163696A1

公开(公告)日：2006-07-27

申请号：US11208561

申请日：2005-08-23

申请人： Kazuhiro Mochizuki ,  Shigehisa Tanaka ,  Tomonori Tanoue

发明人： Kazuhiro Mochizuki ,  Shigehisa Tanaka ,  Tomonori Tanoue

IPC分类号： H01L27/082

CPC分类号： H01L29/7606 ,  H01L29/2003

摘要： The most important task in realizing a downsized and low cost THz band spectroscopic and fluoroscopic instrument is to achieve downsizing and cost reduction of oscillators used in the instrument. A metal base transistor is used for an active element of the oscillator. In order to improve the maximum oscillation frequency of the transistor to several THZ, InN having a high electron saturation velocity or a material mainly composed of InN is used for a collector layer. In order to obtain characteristics with excellent reproducibility, it is useful to insert InGaN into an interface between the collector layer and the base layer. Using the metal base transistor of the present invention makes it possible to constitute an oscillator allowing a THz band oscillation. Further, the present invention provides a spectroscopic instrument applying this oscillator to at least one of a signal source and a local oscillator.

摘要翻译： 实现小型化，低成本的太赫兹频带光谱和荧光检测仪器最重要的任务是实现仪器中使用的振荡器的小型化和降低成本。 金属基极晶体管用于振荡器的有源元件。 为了将晶体管的最大振荡频率提高到几个THZ，具有高电子饱和速度的InN或主要由InN组成的材料用于集电极层。 为了获得具有优异再现性的特性，将InGaN插入到集电极层和基极层之间的界面是有用的。 使用本发明的金属基极晶体管可以构成允许THz频带振荡的振荡器。 此外，本发明提供了一种将该振荡器应用于信号源和本地振荡器中的至少一个的分光仪器。

公开(公告)号：US07276744B2

公开(公告)日：2007-10-02

申请号：US11316908

申请日：2005-12-27

申请人： Kenichi Tanaka ,  Tomonori Tanoue ,  Hidetoshi Matsumoto ,  Hiroshi Ohta ,  Kazuhiro Mochizuki ,  Hiroyuki Uchiyama

发明人： Kenichi Tanaka ,  Tomonori Tanoue ,  Hidetoshi Matsumoto ,  Hiroshi Ohta ,  Kazuhiro Mochizuki ,  Hiroyuki Uchiyama

IPC分类号： H01L29/33 ,  H01L31/109

CPC分类号： H01L29/7371 ,  H01L29/66318

摘要： This invention is intended to provide an HBT capable of achieving, if the HBT is a collector-up HBT, the constriction of the emitter layer disposed directly under an external base layer, and reduction in base-emitter junction capacity, or if the HBT is an emitter-up HBT, reduction in base-collector junction capacity. For the collector-up HBT, window structures around the sidewalls of a collector are used to etch either the emitter layer disposed directly under the external base layer, or an emitter contact layer For the emitter-up HBT, window structures around the sidewalls of an emitter are used to etch either the collector layer disposed directly under the external base layer, or a collector contact layer. In both HBTs, the external base layer is supported by a columnar structure to ensure mechanical strength.

摘要翻译： 本发明旨在提供一种如果HBT是集电极HBT，则可以实现直接位于外部基极层下方的发射极层的收缩，以及基极 - 发射极结能量的降低，或HBT为 发射极HBT，基极 - 集电极结电容降低。 对于收集器HBT，围绕集电极侧壁的窗口结构用于蚀刻直接位于外部基极层下方的发射极层或发射极接触层。对于发射极上升HBT，围绕侧壁的窗口结构 发射极用于蚀刻直接位于外部基底层下方的集电极层或集电极接触层。 在两个HBT中，外部基层由柱状结构支撑以确保机械强度。

公开(公告)号：US5949097A

公开(公告)日：1999-09-07

申请号：US932939

申请日：1997-09-17

申请人： Koji Hirata ,  Tomonori Tanoue ,  Hiroshi Masuda ,  Hiroyuki Uchiyama ,  Kazuhiro Mochizuki

发明人： Koji Hirata ,  Tomonori Tanoue ,  Hiroshi Masuda ,  Hiroyuki Uchiyama ,  Kazuhiro Mochizuki

IPC分类号： H01L21/331 ,  H01L21/768 ,  H01L27/06 ,  H01L29/737 ,  H01L29/04

CPC分类号： H01L29/66318 ,  H01L27/0605 ,  H01L29/7371

摘要： The present invention relates to a contact structure not only for a semiconductor device having a hetero-junction bipolar transistor or a hetero-insulated gate field effect transistor but also for semiconductor devices at large. In a semiconductor layer of a polycrystalline or amorphous undoped III-V compound semiconductor or an alloy thereof, a through hole is formed for contact. The size of the through hole is set to permit exposure of at least part of a first conductor layer and a dielectric layer, such as an Si compound, present around the first conductor layer, and a second conductor layer is formed within the through hole so as to contact the first conductor layer. Since the semiconductor layer can be subjected to a selective dry etching for the dielectric layer, the dielectric layer is not etched at the time of forming the above through hole in the semiconductor layer. As a result an electric short-circuit of the second conductor layer with a single crystal semiconductor layer which underlies the dielectric layer can be prevented.

摘要翻译： 本发明涉及不仅具有异质结双极晶体管或异质绝缘栅场效应晶体管的半导体器件的接触结构，而且还涉及用于半导体器件的半导体器件。 在多晶或非晶未掺杂的III-V族化合物半导体的半导体层或其合金中，形成用于接触的通孔。 通孔的尺寸被设定为允许暴露在第一导体层周围的第一导体层和诸如Si化合物的电介质层的至少一部分，并且在通孔内形成第二导体层，因此 以接触第一导体层。 由于可以对半导体层进行电介质层的选择性干蚀刻，所以在形成半导体层中的上述通孔时不会蚀刻电介质层。 结果，可以防止具有位于电介质层下面的单晶半导体层的第二导体层的电短路。

公开(公告)号：US5017517A

公开(公告)日：1991-05-21

申请号：US518035

申请日：1990-05-02

申请人： Kazuhiro Mochizuki ,  Tomonori Tanoue ,  Chushirou Kusano ,  Hiroshi Masuda ,  Katsuhiko Mitani

发明人： Kazuhiro Mochizuki ,  Tomonori Tanoue ,  Chushirou Kusano ,  Hiroshi Masuda ,  Katsuhiko Mitani

IPC分类号： H01L29/73 ,  H01L21/20 ,  H01L21/28 ,  H01L21/331 ,  H01L29/205 ,  H01L29/737 ,  H01L29/80

CPC分类号： H01L29/66318 ,  H01L21/02395 ,  H01L21/02463 ,  H01L21/02491 ,  H01L21/02546 ,  H01L21/02639 ,  H01L21/28 ,  Y10S148/005 ,  Y10S148/011 ,  Y10S148/026 ,  Y10S438/976

摘要： A method for fabricating a semiconductor device comprises the steps of forming the first semiconductor layer on a semiconductor substrate, forming a surface protection layer of antimony (Sb) or the material having Sb as its main component, executing the other steps necessary for the fabrication of the semiconductor device, removing the surface protection layer, and forming, on the first semiconductor layer thus exposed, the second semiconductor layer.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在半导体衬底上形成第一半导体层，形成锑（Sb）的表面保护层或具有Sb的材料作为其主要成分，执行制造所需的其它步骤 半导体器件，去除表面保护层，并且在由此暴露的第一半导体层上形成第二半导体层。