公开(公告)号：US08902654B2

公开(公告)日：2014-12-02

申请号：US13420767

申请日：2012-03-15

申请人： Hiroshi Maejima ,  Koji Hosono

发明人： Hiroshi Maejima ,  Koji Hosono

IPC分类号： G11C16/08 ,  G11C16/10 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C16/0483

摘要： In a writing operation, a control circuit raises the voltage of a writing-prohibited bit line among a plurality of bit lines to a first voltage, and thereafter brings the writing-prohibited bit line into a floating state. Then, the control circuit raises the voltage of a writing bit line other than the writing-prohibited bit line to a second voltage. In this way, the control circuit prohibits writing into a memory transistor corresponding to the writing-prohibited bit line. On the other hand, the control circuit executes writing into a memory transistor corresponding to the writing bit line.

摘要翻译： 在写入操作中，控制电路将多个位线之间的禁止写入位线的电压提高到第一电压，然后使写入禁止位线处于浮置状态。 然后，控制电路将写入禁止位线以外的写入位线的电压提高到第二电压。 以这种方式，控制电路禁止写入对应于禁止写入位线的存储晶体管。 另一方面，控制电路对与写入位线对应的存储晶体管执行写入。

公开(公告)号：US08717801B2

公开(公告)日：2014-05-06

申请号：US13195417

申请日：2011-08-01

申请人： Hiroshi Maejima ,  Koji Hosono

发明人： Hiroshi Maejima ,  Koji Hosono

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0066

摘要： A memory-cell array that includes a first line, a second line intersecting the first line, and a memory cell including a variable resistive element provided in the intersection of the first and the second lines; a data-write unit configured to apply a voltage pulse to the memory cell through the first and the second lines, the voltage pulse to set and/or reset data; and a detector unit configured to compare a cell current that flows through the memory cell by the voltage pulse at the time of setting and/or resetting the data with a reference current generated from the initial value of the cell current, and to control the data-write unit in accordance with a result of comparison.

摘要翻译： 包括第一行，与第一行相交的第二行的存储单元阵列和包括设置在第一和第二行的交叉点中的可变电阻元件的存储单元; 数据写入单元，被配置为通过第一和第二线路向存储器单元施加电压脉冲，电压脉冲以设置和/或复位数据; 以及检测器单元，被配置为将通过存储器单元流动的单元电流与在从单元电流的初始值生成的参考电流进行设置和/或重置数据时的电压脉冲进行比较，并且控制数据 根据比较结果写入单元。

公开(公告)号：US20130250683A1

公开(公告)日：2013-09-26

申请号：US13603893

申请日：2012-09-05

申请人： Koji HOSONO

发明人： Koji HOSONO

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5671 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

摘要： According to one embodiment, a semiconductor memory device includes memory units each includes a first transistor, memory cell transistors, and a second transistor serially coupled between first and second ends. A memory cell transistor of each memory unit has its gate electrode coupled to each other. A bit line is coupled to the first ends. First and second drivers output voltage applied to selected and unselected first transistors, respectively. Third and fourth drivers output voltage applied to selected and unselected second transistors, respectively. A selector couples the gate electrode of the first transistor of each memory unit to the first or second driver, and that of the second transistor of each memory unit to the third or fourth driver.

公开(公告)号：US20130083597A1

公开(公告)日：2013-04-04

申请号：US13423610

申请日：2012-03-19

申请人： Dai NAKAMURA ,  Koji Hosono ,  Hidehiro Shiga

发明人： Dai NAKAMURA ,  Koji Hosono ,  Hidehiro Shiga

IPC分类号： G11C16/28 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/06 ,  G11C16/16 ,  G11C16/28

摘要： According to one embodiment, a semiconductor memory device includes first and second select transistors, memory cells, a driver circuit, first transfer transistors, and a detection circuit. The memory cells are stacked above a semiconductor substrate. The driver circuit outputs a first voltage. The first transfer transistors transfer the first voltage to associated word lines and select gate lines. In data erase, the detection circuit detects a second voltage applied to bit lines and/or a source line and generates a flag in accordance with the detection result. The driver circuit changes the value of the first voltage in response to the flag to cut off the first transfer transistors.

摘要翻译： 根据一个实施例，半导体存储器件包括第一和第二选择晶体管，存储单元，驱动电路，第一传输晶体管和检测电路。 存储单元堆叠在半导体衬底之上。 驱动电路输出第一电压。 第一传输晶体管将第一电压转移到相关联的字线并选择栅极线。 在数据擦除中，检测电路检测施加到位线和/或源极线的第二电压，并根据检测结果生成标志。 驱动电路响应于标志来改变第一电压的值以切断第一转移晶体管。

公开(公告)号：US08335125B2

公开(公告)日：2012-12-18

申请号：US13285099

申请日：2011-10-31

申请人： Takeshi Nakano ,  Hiroshi Nakamura ,  Koji Hosono

发明人： Takeshi Nakano ,  Hiroshi Nakamura ,  Koji Hosono

IPC分类号： G11C8/00

CPC分类号： G11C16/08

摘要： A semiconductor memory device includes a transfer circuit and a control circuit. The transfer circuit which includes a p-type MOS transistor with a source to which is applied a first voltage and an n-type MOS transistor to whose gate the drain of the p-type MOS transistor is connected and the first voltage is transferred, to whose source a second voltage is applied, and whose drain is connected to a load. The control circuit which turns the p-type MOS transistor on and off and which turns the p-type MOS transistor on to make the p-type MOS transistor transfer the second voltage to the load and, during the transfer, turns the p-type MOS transistor off to make the gate of the n-type MOS transistor float at the first voltage.

摘要翻译： 半导体存储器件包括转移电路和控制电路。 该传输电路包括一个p型MOS晶体管，其源极被施加第一电压，一个n型MOS晶体管被连接到p型MOS晶体管的漏极并且第一个电压被传输到其栅极，到 其源极施加第二电压，并且其漏极连接到负载。 控制电路使p型MOS晶体管导通和关断，并使p型MOS晶体管导通，使p型MOS晶体管将第二电压转移到负载，并且在传输期间使p型MOS晶体管转换为p型 MOS晶体管关闭，使n型MOS晶体管的栅极浮在第一电压。

公开(公告)号：US20120155149A1

公开(公告)日：2012-06-21

申请号：US13407155

申请日：2012-02-28

申请人： Hiroshi Maejima ,  Koji Hosono

发明人： Hiroshi Maejima ,  Koji Hosono

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/00 ,  G11C13/0004 ,  G11C2213/71 ,  G11C2213/72

摘要： A semiconductor storage device includes: a cell array including a plurality of first wirings, a plurality of second wirings intersecting the first wirings, and memory cells positioned at intersecting portions between the first wirings and the second wirings, each of the memory cells having a series circuit of a non-ohmic element and a variable resistance element; a control circuit configured to apply a control voltage, which is necessary for the variable resistance element to transit from a low resistance state to a high resistance state, to the memory cells through the first wirings and the second wirings; and a bias voltage application circuit configured to apply a bias voltage, which suppresses a potential variation caused by the transition of the variable resistance element from the low resistance state to the high resistance state, to one end of the variable resistance element.

摘要翻译： 半导体存储装置包括：包括多个第一布线的多个第一布线，与第一配线相交的多条第二布线和位于第一布线与第二布线之间的交叉部分的存储单元的单元阵列，每个存储单元具有串联 非欧姆元件和可变电阻元件的电路; 控制电路，被配置为通过第一布线和第二布线将可变电阻元件所需的控制电压从低电阻状态转移到高电阻状态; 以及偏置电压施加电路，被配置为将可变电阻元件从低电阻状态向高电阻状态的转变引起的电位变化施加到可变电阻元件的一端。

公开(公告)号：US08174891B2

公开(公告)日：2012-05-08

申请号：US12917813

申请日：2010-11-02

申请人： Koji Hosono

发明人： Koji Hosono

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/3418 ,  G11C16/3427

摘要： A non-volatile semiconductor memory device includes a NAND cell unit including a plurality of electrically rewritable non-volatile memory cells serially connected. The NAND cell unit has one end connected to a bit line via a first selection gate transistor and the other end connected to a source line via a second selection gate transistor. The non-volatile semiconductor memory device also includes a first dummy cell interposed next to the first selection gate transistor in the NAND cell unit. The non-volatile semiconductor memory device additionally includes a second dummy cell interposed next to the second selection gate transistor in the NAND cell unit. In a data write mode, a first voltage applied to a gate of the first dummy cell is higher than or equal to a second voltage applied to a gate of the second dummy cell.

摘要翻译： 非易失性半导体存储器件包括：包括串联连接的多个电可重写非易失性存储单元的NAND单元单元。 NAND单元单元的一端经由第一选择栅极晶体管连接到位线，另一端经由第二选择栅极晶体管连接到源极线。 非易失性半导体存储器件还包括在NAND单元单元中插在第一选择栅晶体管旁边的第一虚设单元。 非易失性半导体存储器件还包括在NAND单元单元中插在第二选择栅极晶体管旁边的第二虚设单元。 在数据写入模式中，施加到第一虚拟单元的栅极的第一电压高于或等于施加到第二虚设单元的栅极的第二电压。

公开(公告)号：US08000155B2

公开(公告)日：2011-08-16

申请号：US13005582

申请日：2011-01-13

申请人： Toshiaki Edahiro ,  Kazushige Kanda ,  Naoya Tokiwa ,  Takuya Futatsuyama ,  Koji Hosono ,  Shigeo Ohshima

发明人： Toshiaki Edahiro ,  Kazushige Kanda ,  Naoya Tokiwa ,  Takuya Futatsuyama ,  Koji Hosono ,  Shigeo Ohshima

IPC分类号： G11C7/22 ,  G11C7/06 ,  G11C11/00 ,  G11C17/00

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/72

摘要： The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.

公开(公告)号：US20110090742A1

公开(公告)日：2011-04-21

申请号：US12981163

申请日：2010-12-29

申请人： Hiroshi NAKAMURA ,  Kenichi Imamiya ,  Toshio Yamamura ,  Koji Hosono ,  Koichi Kawai

发明人： Hiroshi NAKAMURA ,  Kenichi Imamiya ,  Toshio Yamamura ,  Koji Hosono ,  Koichi Kawai

IPC分类号： G11C16/04

CPC分类号： G11C16/3459 ,  G06F3/0659 ,  G06F12/0246 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1063 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C2207/104 ,  G11C2216/14

摘要： In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.

摘要翻译： 在半导体集成电路中，内部电路能够同时执行第一操作和第二操作，并且输出电路向半导体集成电路的外部输出指示是否正在执行第一操作的信息以及指示是否 或者不是第二操作是可执行的。

公开(公告)号：US07916547B2

公开(公告)日：2011-03-29

申请号：US12209486

申请日：2008-09-12

申请人： Koji Hosono

发明人： Koji Hosono

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3454 ,  G11C2211/565

摘要： A non-volatile semiconductor memory device has a NAND string, in which multiple memory cells are connected in series. A read procedure is performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a selected voltage while unselected memory cells are driven to be turned on without regard to cell data thereof. In the read procedure, a first read pass voltage is applied to unselected memory cells except an adjacent and unselected memory cell disposed adjacent to the selected memory cell, the adjacent and unselected memory cell being completed in data write later than the selected memory cell, and a second read pass voltage higher than the first read pass voltage is applied to the adjacent and unselected memory cell.

摘要翻译： 非易失性半导体存储器件具有串联多个存储单元的NAND串。 在所选择的存储单元被施加选定电压的同时驱动未选择的存储单元而不考虑其单元数据的情况下，对NAND串中的所选存储单元执行读取过程。 在读取过程中，第一读取通过电压被施加到非选择存储单元，除了邻近所选存储单元设置的相邻和非选择存储单元之外，相邻和未选择的存储单元在比所选择的存储器单元晚的数据写入中完成;以及 将高于第一读通过电压的第二读通过电压施加到相邻和未选择的存储单元。