公开(公告)号：US09713203B2

公开(公告)日：2017-07-18

申请号：US13424337

申请日：2012-03-19

Applicant: Krishnakumar Mani

Inventor： Krishnakumar Mani

IPC: H05B6/10 ,  H01L21/67

CPC classification number: H05B6/10 ,  H01L21/67109 ,  H01L21/6719

Abstract: In one embodiment of the invention, there is provided a tool for annealing a magnetic stack. The tool includes a housing defining a heating chamber; a holding mechanism to hold at least one wafer in a single line within the heating chamber, a heating mechanism to heat the at least one wafer; and a magnetic field generator to generate a magnetic field whose field lines pass through the single line of wafers during a magnetic annealing process; wherein the holding mechanism comprises a wafer support of holding the single line of wafers between the heating mechanism and the magnetic field generator. The tool may be a rapid thermal processor retrofitted with the magnetic field generator.

公开(公告)号：US09047963B2

公开(公告)日：2015-06-02

申请号：US12202429

申请日：2008-09-01

Applicant: Krishnakumar Mani

Inventor： Krishnakumar Mani

IPC: G11C11/16 ,  B82Y10/00 ,  G11C13/02

CPC classification number: G11C11/16 ,  B82Y10/00 ,  G11C11/161 ,  G11C11/1659 ,  G11C13/025 ,  G11C2213/81

Abstract: A novel magnetic memory cell utilizing nanotubes as conducting leads. The magnetic memory cell may be built based on MTJ (Magnetic Tunnel Junction) or GMR (Giant Magneto Resistance) sensors or devices of similar nature. A SET (Single Electron Transistor) made of semiconducting nanotubes may be used as access devices and/or to build peripheral circuitry.

Abstract translation: 一种利用纳米管作为导线的新型磁记忆体。 磁存储单元可以基于MTJ（磁隧道结）或GMR（巨磁阻）传感器或类似性质的装置来构建。 可以使用由半导体纳米管制成的SET（单电子晶体管）作为存取装置和/或构建外围电路。

公开(公告)号：US20150055410A1

公开(公告)日：2015-02-26

申请号：US13153471

申请日：2011-06-06

Applicant: Krishnakumar Mani

Inventor： Krishnakumar Mani

IPC: G11C11/14

CPC classification number: G11C11/14 ,  G11C7/14 ,  G11C7/24 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1695 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08

Abstract: Memory circuit and method for at least partially dissipating an external magnetic field before the magnetic field affects operation of an array of addressable magnetic storage element stacks in the memory circuit. Multiple dummy magnetic storage element stacks are provided around the periphery of the array. Each of the dummy stacks is substantially circular for orienting along the external magnetic field, thereby causing the dissipation. Each of the addressable and the dummy stacks may be formed with a magnetic tunnel junction (MTJ).

Abstract translation: 用于在磁场影响存储器电路中的可寻址磁存储元件堆阵列的操作之前至少部分耗散外部磁场的存储器电路和方法。 围绕阵列周边设置多个虚拟磁存储元件堆叠。 每个虚拟堆叠基本上是圆形的，用于沿着外部磁场定向，从而导致耗散。 可寻址和虚拟堆叠中的每一个可以形成有磁性隧道结（MTJ）。

公开(公告)号：US20150021724A1

公开(公告)日：2015-01-22

申请号：US13444805

申请日：2012-04-11

Applicant: Krishnakumar Mani

Inventor： Krishnakumar Mani

IPC: H01L43/02

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L27/222 ,  H01L43/08

Abstract: Embodiments of the invention disclose magnetic memory cell configurations in which a magnetic storage structure is coupled to an upper metal layer with minimal overlay margin. This greatly reduces a size of the memory cell.

Abstract translation: 本发明的实施例公开了磁存储单元配置，其中磁存储结构以最小的覆盖裕度耦合到上金属层。 这大大减小了存储单元的大小。

公开(公告)号：US07894252B2

公开(公告)日：2011-02-22

申请号：US12690049

申请日：2010-01-19

Applicant: Krishnakumar Mani

Inventor： Krishnakumar Mani

IPC: G11C11/00

CPC classification number: G01R33/091 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673

Abstract: A magnetic memory cell in which a sensor is magnetically coupled to a magnetic media wherein the separation of the magnetic media from the sensor permits each to be magnetically optimized separate from the other, thus improving defect tolerance and minimizing the magnetic influence of neighboring cells in an array on one another. In an embodiment, the read circuitry is positioned so that no read current passes through the media during a read operation. In an alternative embodiment, processing is simplified but the read current is allowed to pass through the media.

Abstract translation: 一种磁性存储单元，其中传感器磁耦合到磁介质，其中磁介质与传感器的分离允许每个磁性介质与其他磁体分离，从而提高缺陷容限并最小化邻近单元的磁影响 阵列在另一个。 在一个实施例中，读取电路被定位成使得在读取操作期间没有读取电流通过介质。 在替代实施例中，简化了处理，但允许读取电流通过介质。

公开(公告)号：US20100220524A1

公开(公告)日：2010-09-02

申请号：US12714401

申请日：2010-02-26

Applicant: Krishnakumar Mani ,  Jannier Maximo Roiz Wilson ,  Kimihiro Satoh

Inventor： Krishnakumar Mani ,  Jannier Maximo Roiz Wilson ,  Kimihiro Satoh

IPC: G11C11/14 ,  H01L21/00

CPC classification number: H01L27/222 ,  G11C11/1659 ,  G11C11/1675

Abstract: Disclosed is a nonvolatile magnetic memory cell, comprising: a) a switchable magnetic element; b) a word line and a bit line to energize the switchable magnetic element; and c) a magnetic field boosting material positioned adjacent to at least one of the word line and the bit line to boost a magnetic field generated by current flowing therein.

Abstract translation: 公开了一种非易失性磁存储单元，包括：a）可切换磁性元件; b）字线和位线，以激励可切换的磁性元件; 以及c）与所述字线和所述位线中的至少一个相邻定位的磁场增强材料，以增加在其中流动的电流产生的磁场。

公开(公告)号：US20090141542A1

公开(公告)日：2009-06-04

申请号：US11949693

申请日：2007-12-03

Applicant: Krishnakumar Mani ,  Jannier Maximo Roiz Wilson ,  Anil Gupta ,  Kimihiro Satoh

Inventor： Krishnakumar Mani ,  Jannier Maximo Roiz Wilson ,  Anil Gupta ,  Kimihiro Satoh

IPC: G11C11/02

CPC classification number: G11C11/15 ,  G11C7/18 ,  Y10S977/935

Abstract: Embodiments of the present invention disclose an MRAM device having a plurality of magnetic memory cells grouped into words, and write conductors for carrying write currents to write to the memory cells, wherein at least some of the write conductors have a reduced cross-sectional area in the vicinity of a group of memory cells.

Abstract translation: 本发明的实施例公开了一种具有分组成多个磁存储器单元的MRAM器件和用于承载写入电流以写入存储器单元的写导体，其中写入导体中的至少一些具有减小的横截面积 一组存储单元的附近。

公开(公告)号：US09395410B2

公开(公告)日：2016-07-19

申请号：US13153472

申请日：2011-06-06

Applicant: Krishnakumar Mani

Inventor： Krishnakumar Mani

IPC: G01R27/08 ,  G01R31/28 ,  G01R31/30 ,  G11C5/00 ,  H01F1/00 ,  H01L21/00

CPC classification number: G01R31/2884 ,  G01R31/3004 ,  G11C5/00 ,  G11C5/005 ,  G11C11/1673 ,  G11C11/1677 ,  G11C29/50008 ,  G11C29/52 ,  H01F1/00 ,  H01L21/00

Abstract: Integrated circuit comprising a sensing unit that includes a sensing circuit, two conductors and a magnetic storage element. The sensing circuit monitors a voltage drop across the element when a current is passed between the conductors with the element in between. The voltage drop is pre-calibrated to indicate a change in conductivity in the element that is caused by an external magnetic field. Advantageously, this indication is usable particularly for assessing a possible data corruption in a magnetic memory circuit in the integrated circuit, due to stray and external magnetic fields. Methods of using the sensing unit are also proposed.

Abstract translation: 集成电路包括感测单元，其包括感测电路，两个导体和磁存储元件。 当电流在导体之间通过元件之间时，感测电路监测元件两端的电压降。 电压降被预校准，以指示由外部磁场引起的元件中的电导率的变化。 有利地，该指示特别用于评估由于杂散和外部磁场而导致的集成电路中的磁存储器电路中可能的数据损坏。 还提出了使用感测单元的方法。

公开(公告)号：US08879306B2

公开(公告)日：2014-11-04

申请号：US13208577

申请日：2011-08-12

Applicant: Krishnakumar Mani

Inventor： Krishnakumar Mani

IPC: G11C11/00

CPC classification number: H01L43/12 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675 ,  H01L43/02 ,  H01L43/08

Abstract: Memory circuit comprising an addressable magnetic tunnel junction (MTJ) stack, forming a magnetic storage element in the circuit. The MTJ stack comprises a tunnel oxide layer between a free layer and a fixed layer. A stress inducing layer is disposed adjacent to the free layer to provide tensile or compressive stress to the free layer, in order to manipulate a magnetic field that is required to write a bit into the MTJ stack. Method of using the memory circuit is also proposed.

Abstract translation: 存储器电路包括可寻址磁隧道结（MTJ）堆叠，在电路中形成磁存储元件。 MTJ堆叠包括在自由层和固定层之间的隧道氧化物层。 应力诱导层邻近自由层设置以向自由层提供拉伸或压缩应力，以便操纵将位写入MTJ堆叠所需的磁场。 还提出了使用存储器电路的方法。

公开(公告)号：US20140301138A1

公开(公告)日：2014-10-09

申请号：US13153473

申请日：2011-06-06

Applicant: Krishnakumar Mani

Inventor： Krishnakumar Mani

IPC: G11C11/14 ,  H01L29/82 ,  H01L21/8239

CPC classification number: G11C11/1673 ,  G11C11/14 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/36 ,  H01L27/222 ,  H01L27/224 ,  H01L27/228 ,  H01L29/872 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Memory cell comprising two conductors, with a serially connected magnetic storage element and a Schottky diode between the two conductors. The Schottky diode provides a unidirectional conductive path between the two conductors and through the element. The Schottky diode is formed between a metal layer in one of the two conductors and a processed junction layer. Methods for process and for operation of the memory cell are also disclosed. The memory cell using the Schottky diode can be designed for high speed operation and with high density of integration. Advantageously, the junction layer can also be used as a hard mask for defining the individual magnetic storage element in the memory cell. The memory cell is particularly useful for magnetic random access memory (MRAM) circuits.

Abstract translation: 存储单元包括两个导体，在两个导体之间具有串联连接的磁存储元件和肖特基二极管。 肖特基二极管在两个导体之间提供一个单向的导电路径，并通过该元件。 肖特基二极管形成在两个导体中的一个中的金属层和经处理的接合层之间。 还公开了用于存储器单元的处理和操作的方法。 使用肖特基二极管的存储单元可以设计用于高速运行和高密度集成。 有利地，接合层也可以用作硬掩模，用于限定存储单元中的各个磁存储元件。 存储单元对磁性随机存取存储器（MRAM）电路特别有用。