公开(公告)号：US08697515B2

公开(公告)日：2014-04-15

申请号：US13490108

申请日：2012-06-06

申请人： Joanna Chaw Yane Yin ,  Chi-Hsi Wu ,  Kuo-Chiang Ting ,  Kuang-Hsin Chen

发明人： Joanna Chaw Yane Yin ,  Chi-Hsi Wu ,  Kuo-Chiang Ting ,  Kuang-Hsin Chen

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/66 ,  H01L27/088

CPC分类号： H01L21/823481 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/6681

摘要： The present disclosure provides many different embodiments of fabricating a FinFET device that provide one or more improvements over the prior art. In one embodiment, a method of fabricating a FinFET includes providing a semiconductor substrate and a plurality of dummy fins and active fins on the semiconductor substrate. A predetermined group of dummy fins is removed.

摘要翻译： 本公开提供了制造FinFET器件的许多不同实施例，其提供了超过现有技术的一个或多个改进。 在一个实施例中，制造FinFET的方法包括在半导体衬底上提供半导体衬底和多个虚拟鳍片和活动鳍片。 去除预定组的虚拟翅片。

公开(公告)号：US20130330889A1

公开(公告)日：2013-12-12

申请号：US13490108

申请日：2012-06-06

申请人： Joanna ChawYane Yin ,  Chi-Hsi Wu ,  Kuo-Chiang Ting ,  Kuang-Hsin Chen

发明人： Joanna ChawYane Yin ,  Chi-Hsi Wu ,  Kuo-Chiang Ting ,  Kuang-Hsin Chen

IPC分类号： H01L21/336 ,  H01L21/02

CPC分类号： H01L21/823481 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/6681

摘要： The present disclosure provides many different embodiments of fabricating a FinFET device that provide one or more improvements over the prior art. In one embodiment, a method of fabricating a FinFET includes providing a semiconductor substrate and a plurality of dummy fins and active fins on the semiconductor substrate. A predetermined group of dummy fins is removed.

摘要翻译： 本公开提供了制造FinFET器件的许多不同实施例，其提供了超过现有技术的一个或多个改进。 在一个实施例中，制造FinFET的方法包括在半导体衬底上提供半导体衬底和多个虚拟鳍片和活动鳍片。 去除预定组的虚拟翅片。

公开(公告)号：US07986029B2

公开(公告)日：2011-07-26

申请号：US11268914

申请日：2005-11-08

申请人： Chiang-Ming Chuang ,  Kuang-Hsin Chen ,  I-Lu Wu

发明人： Chiang-Ming Chuang ,  Kuang-Hsin Chen ,  I-Lu Wu

IPC分类号： H01L29/06

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/1207 ,  H01L29/045

摘要： A semiconductor structure having a hybrid crystal orientation is provided. The semiconductor structure includes an insulator layer, e.g., a buried oxide (BOX), on a first semiconductor layer, and a second semiconductor layer on the buried oxide, wherein the first and second semiconductor layers have a first and a second crystal orientation, respectively. A first region of the second semiconductor layer is replaced with an epitaxially grown layer of the first semiconductor layer, thereby providing a substrate having a first region with a first crystal orientation and a second region with a second crystal orientation. An isolation structure is formed to isolate the first and second regions. Thereafter, NMOS and PMOS transistors may be formed on the substrate in the region having the crystal orientation that is the most appropriate.

摘要翻译： 提供具有混合晶体取向的半导体结构。 所述半导体结构包括在第一半导体层上的绝缘体层，例如掩埋氧化物（BOX）和所述掩埋氧化物上的第二半导体层，其中所述第一和第二半导体层分别具有第一和第二晶体取向 。 用第一半导体层的外延生长层代替第二半导体层的第一区域，从而提供具有第一晶体取向的第一区域和具有第二晶体取向的第二区域的衬底。 形成隔离结构以隔离第一和第二区域。 此后，可以在具有最合适的晶体取向的区域中的衬底上形成NMOS和PMOS晶体管。

公开(公告)号：US07538351B2

公开(公告)日：2009-05-26

申请号：US11089405

申请日：2005-03-23

申请人： Hung-Wei Chen ,  Hsun-Chih Tsao ,  Kuang-Hsin Chen ,  Di-Hong Lee

发明人： Hung-Wei Chen ,  Hsun-Chih Tsao ,  Kuang-Hsin Chen ,  Di-Hong Lee

IPC分类号： H01L29/10

CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0251 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/7843 ,  H01L29/7851 ,  H01L29/7854

摘要： A semiconductor device and method for forming the same including improved electrostatic discharge protection for advanced semiconductor devices, the semiconductor device including providing semiconductor substrate having a pre-selected surface orientation and crystal direction; an insulator layer overlying the semiconductor substrate; a first semiconductor active region overlying the insulator layer having a first surface orientation selected from the group consisting of and ; a second semiconductor active region extending through a thickness portion of the insulator layer having a second surface orientation selected from the group consisting of and different from the first surface orientation; wherein MOS devices including a first MOS device of a first conduction type is disposed on the first semiconductor active region and a second MOS device of a second conduction type is disposed on the second semiconductor active region.

摘要翻译： 一种半导体器件及其制造方法，包括提供先进半导体器件的改进的静电放电保护，所述半导体器件包括提供具有预选择的表面取向和晶体方向的半导体衬底; 覆盖半导体衬底的绝缘体层; 覆盖绝缘体层的第一半导体有源区具有选自<100>和<110>的第一表面取向; 延伸穿过绝缘体层的厚度部分的第二半导体有源区，其具有选自与第一表面取向不同的<110>和<100>的第二表面取向; 其中包括第一导电类型的第一MOS器件的MOS器件设置在第一半导体有源区上，并且第二导电类型的第二MOS器件设置在第二半导体有源区上。

公开(公告)号：US20080179689A1

公开(公告)日：2008-07-31

申请号：US11669870

申请日：2007-01-31

申请人： Tan-Chen Lee ,  Chung-Te Lin ,  Kuang-Hsin Chen ,  Chi-Hsi Wu ,  Di-Houng Lee ,  Cheng-Hung Chang

发明人： Tan-Chen Lee ,  Chung-Te Lin ,  Kuang-Hsin Chen ,  Chi-Hsi Wu ,  Di-Houng Lee ,  Cheng-Hung Chang

IPC分类号： H01L29/78 ,  H01L21/441

CPC分类号： H01L21/28518 ,  H01L21/76829 ,  H01L29/665

摘要： Disclosed herein are various embodiments of techniques for preventing silicide stringer or encroachment formation during metal salicide formation in semiconductor devices. The disclosed technique involves depositing a protective layer, such as a nitride or other dielectric layer, over areas of the semiconductor device where metal silicide formation is not desired because such formation detrimentally affects device performance. For example, silicon particles that may remain in device features that are formed through silicon oxidation, such as under the gate sidewall spacers and proximate to the perimeter of shallow trench isolation structures, are protected from reacting with metal deposited to form metal silicide in certain areas of the device. As a result, silicide stringers or encroachment in undesired areas is reduced or eliminated by the protective layer.

摘要翻译： 本文公开了用于在半导体器件中的金属自对准硅化物形成期间防止硅化物纵梁或侵入形成的技术的各种实施例。 所公开的技术包括在不需要金属硅化物形成的半导体器件的区域上沉积诸如氮化物或其它电介质层的保护层，因为这种形成不利地影响器件性能。 例如，可以保留在通过硅氧化形成的器件特征中的硅颗粒，例如在栅极侧壁间隔物附近并且靠近浅沟槽隔离结构的周边，防止在某些区域沉积以形成金属硅化物的金属反应 的设备。 结果，通过保护层减少或消除了硅化物桁条或侵入不期望的区域。

公开(公告)号：US20070111425A1

公开(公告)日：2007-05-17

申请号：US11648964

申请日：2007-01-03

申请人： I-Lu Wu ,  Kuang-Hsin Chen ,  Liang-Kai Han

发明人： I-Lu Wu ,  Kuang-Hsin Chen ,  Liang-Kai Han

IPC分类号： H01L21/8238

CPC分类号： H01L21/823842 ,  H01L21/823857 ,  H01L29/785

摘要： An integrated circuit having composite gate structures and a method of forming the same are provided. The integrated circuit includes a first MOS device, a second MOS device and a third MOS device. The gate stack of the first MOS device includes a high-k gate dielectric and a first metal gate on the high-k gate dielectric. The gate stack of the second MOS device includes a second metal gate on a high-k gate dielectric. The first metal gate and the second metal gate have different work functions. The gate stack of the third MOS device includes a silicon gate over a gate dielectric. The silicon gate is preferably formed over the gate stacks of the first MOS device and the second MOS device.

公开(公告)号：US07074692B2

公开(公告)日：2006-07-11

申请号：US10807081

申请日：2004-03-23

申请人： Hung-Wei Chen ,  Hsun-Chin Tsao ,  Kuang-Hsin Chen ,  Di-Houng Lee

发明人： Hung-Wei Chen ,  Hsun-Chin Tsao ,  Kuang-Hsin Chen ,  Di-Houng Lee

IPC分类号： H01L21/76

CPC分类号： H01L21/76243 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78603

摘要： Methods of reducing a short channel phenomena for an NMOS device formed in an SOI layer, wherein the short channel phenomena is created by boron movement from a channel region to adjacent insulator regions, has been developed. A first embodiment of this invention entails the formation of a boron or nitrogen doped insulator layer located underlying the NMOS device. This is accomplished via formation of shallow trench openings in composite silicon nitride-silicon shapes, followed by lateral pull back of the silicon nitride shapes exposing portions of the top surface of the silicon shapes, followed by implantation of boron or nitrogen ions into portions of the insulator layer exposed in the STI openings and into portions of the insulator layer underlying exposed portions of the silicon shapes. A subsequent hydrogen anneal procedure finalizes the doped insulator layer which alleviates boron segregation from an overlying NMOS channel region. A second embodiment features the formation of a dielectric barrier layer on the surfaces of STI openings preventing boron from segregated to silicon oxide filled STI regions. A combination of both embodiments can be employed to reduce and prevent boron segregation to both underlying and adjacent insulator regions, thus reducing the risk of short channel phenomena.

摘要翻译： 已经开发了减少在SOI层中形成的NMOS器件的短通道现象的方法，其中通过硼从沟道区域移动到相邻的绝缘体区域产生短沟道现象。 本发明的第一实施例需要形成位于NMOS器件下面的硼或氮掺杂的绝缘体层。 这是通过在复合氮化硅 - 硅形状中形成浅沟槽开口而实现的，随后氮化硅形状的横向拉回暴露出硅形状的顶表面的部分，然后将硼或氮离子注入到 绝缘体层暴露在STI开口中并且沉积在硅形状的暴露部分下面的绝缘体层的部分中。 随后的氢退火程序完成掺杂的绝缘体层，其减轻了从上覆的NMOS沟道区域的硼偏析。 第二实施例的特征在于在STI开口的表面上形成介电阻挡层，防止硼偏析到填充氧化硅的STI区域。 可以采用两种实施方案的组合来减少和防止硼分离到下面的和相邻的绝缘体区域，从而降低短沟道现象的风险。

公开(公告)号：US20050212015A1

公开(公告)日：2005-09-29

申请号：US10810950

申请日：2004-03-25

申请人： Chien-Chao Huang ,  Kuang-Hsin Chen ,  Fu-Liang Yang

发明人： Chien-Chao Huang ,  Kuang-Hsin Chen ,  Fu-Liang Yang

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/82 ,  H01L21/8234 ,  H01L27/02

CPC分类号： H01L29/66553 ,  H01L21/28097 ,  H01L21/82345 ,  H01L21/823468 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

摘要： A method for manufacturing a metal gate includes providing a substrate including a gate electrode located on the substrate. A plurality of layers is formed, including a first layer located on the substrate and the gate electrode and a second layer adjacent the first layer. The layers are etched to form a plurality of adjacent spacers, including a first spacer located on the substrate and adjacent the gate electrode and a second spacer adjacent the first spacer. The first spacer is then etched and a metal layer is formed on the device immediately adjacent to the gate electrode. The metal layer is then reacted with the gate electrode to form a metal gate.

摘要翻译： 一种用于制造金属栅极的方法包括提供包括位于基板上的栅电极的基板。 形成多个层，包括位于衬底上的第一层和栅电极以及与第一层相邻的第二层。 这些层被蚀刻以形成多个相邻的间隔物，包括位于衬底上并且邻近栅电极的第一间隔物和邻近第一间隔物的第二间隔物。 然后蚀刻第一间隔物，并且在紧邻栅电极的器件上形成金属层。 然后金属层与栅电极反应形成金属栅极。

公开(公告)号：US20050110086A1

公开(公告)日：2005-05-26

申请号：US10720775

申请日：2003-11-24

申请人： Chuan-Ping Hou ,  Jhi-Cherng Lu ,  Kuang-Hsin Chen ,  Hsun-Chih Tsao

发明人： Chuan-Ping Hou ,  Jhi-Cherng Lu ,  Kuang-Hsin Chen ,  Hsun-Chih Tsao

IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L27/01 ,  H01L27/12 ,  H01L29/772

CPC分类号： H01L29/7853 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795

摘要： A method for forming a field effect transistor includes: forming a conductive region on an isolation layer formed on a substrate, and a cap dielectric layer on the conductive region; forming a sacrificial dielectric layer over the isolation layer and the cap dielectric layer, and on sidewalls of the conductive region; removing a portion of the sacrificial dielectric layer on the cap dielectric layer; removing the cap dielectric layer; removing remaining portions of the sacrificial dielectric layer; forming a gate on the conductive region; and forming source/drain (S/D) regions within the conductive region and adjacent to the gate. A field effect transistor includes a conductive region over an isolation layer formed on a substrate, the conductive region being substantially without undercut at the region within the isolation layer beneath the conductive region; a gate on the conductive region; and S/D regions within the conductive region and adjacent to the gate.

摘要翻译： 一种用于形成场效应晶体管的方法，包括：在形成于基板上的隔离层上形成导电区域，在导电区域上形成盖电介质层; 在所述隔离层和所述盖电介质层上以及所述导电区域的侧壁上形成牺牲介电层; 去除所述帽介电层上的牺牲介电层的一部分; 去除所述盖电介质层; 去除牺牲介电层的剩余部分; 在导电区上形成栅极; 以及在所述导电区域内并且邻近所述栅极形成源极/漏极（S / D）区域。 场效应晶体管包括在衬底上形成的隔离层上的导电区域，该导电区域在导电区域下面的隔离层内的区域基本上没有底切; 导电区域上的栅极; 和导电区域内的S / D区域并且与栅极相邻。

公开(公告)号：US07732298B2

公开(公告)日：2010-06-08

申请号：US11669870

申请日：2007-01-31

申请人： Tan-Chen Lee ,  Chung-Te Lin ,  Kuang-Hsin Chen ,  Chi-Hsi Wu ,  Di-Houng Lee ,  Cheng-Hung Chang

发明人： Tan-Chen Lee ,  Chung-Te Lin ,  Kuang-Hsin Chen ,  Chi-Hsi Wu ,  Di-Houng Lee ,  Cheng-Hung Chang

IPC分类号： H01L21/76

CPC分类号： H01L21/28518 ,  H01L21/76829 ,  H01L29/665

摘要： Disclosed herein are various embodiments of techniques for preventing silicide stringer or encroachment formation during metal salicide formation in semiconductor devices. The disclosed technique involves depositing a protective layer, such as a nitride or other dielectric layer, over areas of the semiconductor device where metal silicide formation is not desired because such formation detrimentally affects device performance. For example, silicon particles that may remain in device features that are formed through silicon oxidation, such as under the gate sidewall spacers and proximate to the perimeter of shallow trench isolation structures, are protected from reacting with metal deposited to form metal silicide in certain areas of the device. As a result, silicide stringers or encroachment in undesired areas is reduced or eliminated by the protective layer.

摘要翻译： 本文公开了用于在半导体器件中的金属自对准硅化物形成期间防止硅化物纵梁或侵入形成的技术的各种实施例。 所公开的技术包括在不需要金属硅化物形成的半导体器件的区域上沉积诸如氮化物或其它电介质层的保护层，因为这种形成不利地影响器件性能。 例如，可以保留在通过硅氧化形成的器件特征中的硅颗粒，例如在栅极侧壁间隔物附近并且靠近浅沟槽隔离结构的周边，防止在某些区域沉积以形成金属硅化物的金属反应 的设备。 结果，通过保护层减少或消除了硅化物桁条或侵入不期望的区域。