公开(公告)号：US20150108467A1

公开(公告)日：2015-04-23

申请号：US13996033

申请日：2011-12-15

申请人： Masao Moriguchi ,  Yohsuke Kanzaki ,  Yudai Takanishi ,  Takatsugu Kusumi ,  Hiroshi Matsukizono

发明人： Masao Moriguchi ,  Yohsuke Kanzaki ,  Yudai Takanishi ,  Takatsugu Kusumi ,  Hiroshi Matsukizono

IPC分类号： H01L23/00 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L27/124 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/134372 ,  H01L23/564 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device (100) according to the present invention is a semiconductor device with a thin-film transistor (10), and includes: a gate electrode (62) which has been formed on a substrate (60) as a part of the thin-film transistor (10); a gate insulating layer (66) which has been formed on the gate electrode (62); an oxide semiconductor layer (68) which has been formed on the gate insulating layer (66); a source electrode (70s) and a drain electrode (70d) which have been formed on the oxide semiconductor layer (68); a protective layer (72) which has been formed on the oxide semiconductor layer (68), the source electrode (70s) and the drain electrode (70d); an oxygen supplying layer (74) which has been formed on the protective layer (72); and an anti-diffusion layer (78) which has been formed on the oxygen supplying layer (74).

摘要翻译： 根据本发明的半导体器件（100）是具有薄膜晶体管（10）的半导体器件，包括：栅极电极（62），其形成在基板（60）上，作为薄膜晶体管 - 薄膜晶体管（10）; 已经形成在所述栅极（62）上的栅极绝缘层（66）; 形成在栅极绝缘层（66）上的氧化物半导体层（68）; 形成在所述氧化物半导体层上的源极电极和漏极电极， 形成在氧化物半导体层（68）上的保护层（72），源电极（70s）和漏电极（70d）。 形成在保护层（72）上的供氧层（74）; 和形成在供氧层（74）上的抗扩散层（78）。

公开(公告)号：US08957418B2

公开(公告)日：2015-02-17

申请号：US13992367

申请日：2011-12-06

申请人： Masao Moriguchi ,  Yohsuke Kanzaki ,  Yudai Takanishi ,  Takatsugu Kusumi ,  Hiroshi Matsukizono

发明人： Masao Moriguchi ,  Yohsuke Kanzaki ,  Yudai Takanishi ,  Takatsugu Kusumi ,  Hiroshi Matsukizono

IPC分类号： H01L21/46 ,  H01L27/15 ,  H01L27/12 ,  H01L29/786 ,  H01L29/49 ,  H01L29/66 ,  H01L27/32 ,  G02F1/1368

CPC分类号： H01L27/15 ,  G02F1/1368 ,  H01L21/46 ,  H01L27/1225 ,  H01L27/3262 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869

摘要： A semiconductor device according to the present invention includes: a gate electrode (62) of a thin film transistor (10) and an oxygen supply layer (64), the gate electrode (62) and the oxygen supply layer (64) being formed on a substrate (60); a gate insulating layer (66) formed on the gate electrode (62) and the oxygen supply layer (64); an oxide semiconductor layer (68) of the thin film transistor (10), the oxide semiconductor layer (68) being formed on the gate insulating layer (66); and a source electrode (70S) and a drain electrode (70d) of the thin film transistor (10), the source electrode (70S) and the drain electrode (70d) being formed on the gate insulating layer (66) and the oxide semiconductor layer (68).

摘要翻译： 根据本发明的半导体器件包括：薄膜晶体管（10）的栅电极（62）和氧供给层（64），栅电极（62）和供氧层（64）形成在 基板（60）; 形成在所述栅电极（62）和所述供氧层（64）上的栅绝缘层（66）。 所述薄膜晶体管（10）的氧化物半导体层（68），所述氧化物半导体层（68）形成在所述栅极绝缘层（66）上; 以及所述薄膜晶体管（10）的源电极（70S）和漏电极（70d），所述源极电极（70S）和所述漏极电极（70d）形成在所述栅极绝缘层（66）上，并且所述氧化物半导体 层（68）。

公开(公告)号：US08575615B2

公开(公告)日：2013-11-05

申请号：US13119210

申请日：2009-09-01

申请人： Yuichi Saito ,  Masao Moriguchi ,  Tokuo Yoshida ,  Yasuaki Iwase ,  Yohsuke Kanzaki ,  Mayuko Sakamoto

发明人： Yuichi Saito ,  Masao Moriguchi ,  Tokuo Yoshida ,  Yasuaki Iwase ,  Yohsuke Kanzaki ,  Mayuko Sakamoto

IPC分类号： H01L31/00 ,  H01L29/10 ,  H01L29/04 ,  H01L31/036

CPC分类号： H01L27/12 ,  G02F1/136204 ,  H01L27/1225

摘要： A diode 201 includes a gate electrode 2, a gate insulating layer 5 provided on the gate electrode 2, at least one semiconductor layer 6, 7 provided on the gate insulating layer 5 and which includes a first region 6a and a second region 7b, a first electrode 10 which is provided on the first region 6a and which is electrically coupled to the first region 6a and the gate electrode 2, and a second electrode 12 which is provided on the second region 7b and which is electrically coupled to the second region 7b. The at least one semiconductor layer 6, 7 includes a channel region 6c which extends above the gate electrode 2 with the intervention of the gate insulating layer 5 therebetween, and a resistor region 7d which does not extend above the gate electrode 2. When the diode 201 is in an ON state, an electric current path is formed between the first electrode 10 and the second electrode 12, the electric current path including the channel region 6c and the resistor region 7d.

摘要翻译： 二极管201包括栅极电极2，设置在栅极电极2上的栅极绝缘层5，设置在栅极绝缘层5上的至少一个半导体层6,7，其包括第一区域6a和第二区域7b， 第一电极10设置在第一区域6a上并且电耦合到第一区域6a和栅极电极2;以及第二电极12，其设置在第二区域7b上并且电耦合到第二区域7b 。 至少一个半导体层6,7包括在栅极电极2上方延伸的沟道区域6c，其中介于其间的栅极绝缘层5以及不在栅极电极2上方延伸的电阻器区域7d。当二极管 201处于导通状态，在第一电极10和第二电极12之间形成电流路径，电流路径包括沟道区6c和电阻区7d。

公开(公告)号：US08563406B2

公开(公告)日：2013-10-22

申请号：US12416240

申请日：2009-04-01

申请人： Yutaka Takafuji ,  Yasumori Fukushima ,  Masao Moriguchi

发明人： Yutaka Takafuji ,  Yasumori Fukushima ,  Masao Moriguchi

IPC分类号： H01L21/322

CPC分类号： H01L27/1266 ,  H01L21/76202 ,  H01L21/76254 ,  H01L27/1203 ,  H01L27/1214 ,  H01L29/78603 ,  H01L29/78609

摘要： The present invention provides a semiconductor substrate, which comprises a singlecrystalline Si substrate which includes an active layer having a channel region, a source region, and a drain region, the singlecrystalline Si substrate including at least a part of a device structure not containing a well-structure or a channel stop region; a gate insulating film formed on the singlecrystalline Si substrate; a gate electrode formed on the gate insulating film; a LOCOS oxide film whose thickness is more than a thickness of the gate insulating film, the LOCOS oxide film being formed on the singlecrystalline Si substrate by surrounding the active layer; and an insulating film formed over the gate electrode and the LOCOS oxide film. On this account, on fabricating the semiconductor device having a high-performance integration system by forming the non-singlecrystalline Si semiconductor element and the singlecrystalline Si semiconductor element on the large insulating substrate, the process for making the singlecrystalline Si is simplified. Further, the foregoing arrangement provides a semiconductor substrate and a fabrication method thereof, which ensures device isolation of the minute singlecrystalline Si semiconductor element without highly-accurate photolithography, when the singlecrystalline Si semiconductor element is transferred onto the large insulating substrate.

公开(公告)号：US08440548B2

公开(公告)日：2013-05-14

申请号：US13185742

申请日：2011-07-19

申请人： Hidekazu Miyairi ,  Takashi Ienaga ,  Masao Moriguchi ,  Yosuke Kanzaki

发明人： Hidekazu Miyairi ,  Takashi Ienaga ,  Masao Moriguchi ,  Yosuke Kanzaki

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/32105 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78678 ,  H01L29/78696

摘要： An object is to provide a manufacturing method of a microcrystalline silicon film with improved adhesion between an insulating film and the microcrystalline silicon film. The microcrystalline silicon film is formed in the following manner. Over an insulating film, a microcrystalline silicon grain having a height that allows the microcrystalline silicon grain to be completely oxidized by later plasma oxidation (e.g., a height greater than 0 nm and less than or equal to 5 nm), or a microcrystalline silicon film or an amorphous silicon film having a thickness that allows the microcrystalline silicon film or the amorphous silicon film to be completely oxidized by later plasma oxidation (e.g., a thickness greater than 0 nm and less than or equal to 5 nm) is formed. Plasma treatment in an atmosphere including oxygen or plasma oxidation is performed on the microcrystalline silicon grain, the microcrystalline silicon film, or the amorphous silicon film, so that a silicon oxide grain or a silicon oxide film is formed over the insulating film. A microcrystalline silicon film is formed over the silicon oxide grain or the silicon oxide film.

摘要翻译： 本发明的目的是提供一种具有改善的绝缘膜和微晶硅膜之间的粘附性的微晶硅膜的制造方法。 以下述方式形成微晶硅膜。 在绝缘膜上，具有通过稍后的等离子体氧化（例如，高于0nm且小于或等于5nm的高度）使微晶硅晶粒完全氧化的高度的微晶硅晶粒或微晶硅膜 或具有通过稍后的等离子体氧化（例如，厚度大于0nm且小于或等于5nm）使微晶硅膜或非晶硅膜完全氧化的厚度的非晶硅膜。 在微晶硅晶粒，微晶硅膜或非晶硅膜上进行包括氧或等离子体氧化的气氛中的等离子体处理，使得在绝缘膜上形成氧化硅晶粒或氧化硅膜。 在氧化硅晶粒或氧化硅膜上形成微晶硅膜。

公开(公告)号：US20120273785A1

公开(公告)日：2012-11-01

申请号：US13518564

申请日：2010-11-11

申请人： Masao Moriguchi ,  Yohsuke Kanzaki ,  Tsuyoshi Inoue

发明人： Masao Moriguchi ,  Yohsuke Kanzaki ,  Tsuyoshi Inoue

IPC分类号： H01L31/12 ,  H01L33/08 ,  H01L31/18 ,  H01L31/0248

CPC分类号： H01L27/14692 ,  H01L27/14609

摘要： A photosensor element (6a) is provided with a gate electrode (11da) disposed on an insulating substrate (10), a gate insulating film (12) disposed so as to cover the gate electrode (11da), a semiconductor layer (15db) disposed on the gate insulating film (12) so as to overlap the gate electrode (11da), and a source electrode (16da) and a drain electrode (16db) provided on the semiconductor layer (15db) so as to overlap the gate electrode (11da) and so as to face each other. The photosensor element (6a) has the semiconductor layer (15db) provided with an intrinsic semiconductor layer (13db) in which a channel region (C) is defined and an extrinsic semiconductor layer (14db) that is laminated on the intrinsic semiconductor layer (13db) such that the channel region (C) is exposed. The extrinsic semiconductor layer (14db) protrudes from the drain electrode (16db) on the side close to the channel region (C).

摘要翻译： 光传感器元件（6a）设置有设置在绝缘基板（10）上的栅电极（11da），设置为覆盖栅电极（11da）的栅极绝缘膜（12），设置有半导体层 在所述栅极绝缘膜（12）上与所述栅电极（11da）重叠，以及设置在所述半导体层（15db）上的源极电极（16da）和漏电极（16db），以与所述栅电极（11da）重叠 ），以便彼此面对。 光电传感器元件（6a）具有设置有限定沟道区（C）的本征半导体层（13db）的半导体层（15db）和层叠在本征半导体层（13db）上的非本征半导体层（14db） ），使得沟道区域（C）暴露。 外部半导体层（14db）在靠近沟道区域（C）的一侧从漏电极（16db）突出。

公开(公告)号：US20120034765A1

公开(公告)日：2012-02-09

申请号：US13185742

申请日：2011-07-19

申请人： Hidekazu MIYAIRI ,  Takashi IENAGA ,  Masao MORIGUCHI ,  Yosuke KANZAKI

发明人： Hidekazu MIYAIRI ,  Takashi IENAGA ,  Masao MORIGUCHI ,  Yosuke KANZAKI

IPC分类号： H01L21/20

CPC分类号： H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/32105 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78678 ,  H01L29/78696

摘要： An object is to provide a manufacturing method of a microcrystalline silicon film with improved adhesion between an insulating film and the microcrystalline silicon film. The microcrystalline silicon film is formed in the following manner. Over an insulating film, a microcrystalline silicon grain having a height that allows the microcrystalline silicon grain to be completely oxidized by later plasma oxidation (e.g., a height greater than 0 nm and less than or equal to 5 nm), or a microcrystalline silicon film or an amorphous silicon film having a thickness that allows the microcrystalline silicon film or the amorphous silicon film to be completely oxidized by later plasma oxidation (e.g., a thickness greater than 0 nm and less than or equal to 5 nm) is formed. Plasma treatment in an atmosphere including oxygen or plasma oxidation is performed on the microcrystalline silicon grain, the microcrystalline silicon film, or the amorphous silicon film, so that a silicon oxide grain or a silicon oxide film is formed over the insulating film. A microcrystalline silicon film is formed over the silicon oxide grain or the silicon oxide film.

摘要翻译： 本发明的目的是提供一种具有改善的绝缘膜和微晶硅膜之间的粘附性的微晶硅膜的制造方法。 以下述方式形成微晶硅膜。 在绝缘膜上，具有通过稍后的等离子体氧化（例如，高于0nm且小于或等于5nm的高度）使微晶硅晶粒完全氧化的高度的微晶硅晶粒或微晶硅膜 或具有通过稍后的等离子体氧化（例如，厚度大于0nm且小于或等于5nm）使微晶硅膜或非晶硅膜完全氧化的厚度的非晶硅膜。 在微晶硅晶粒，微晶硅膜或非晶硅膜上进行包括氧或等离子体氧化的气氛中的等离子体处理，使得在绝缘膜上形成氧化硅晶粒或氧化硅膜。 在氧化硅晶粒或氧化硅膜上形成微晶硅膜。

公开(公告)号：US20100283103A1

公开(公告)日：2010-11-11

申请号：US12745497

申请日：2008-11-14

申请人： Michiko Takei ,  Yasumori Fukushima ,  Kazuhide Tomiyasu ,  Masao Moriguchi ,  Yutaka Takafuji

发明人： Michiko Takei ,  Yasumori Fukushima ,  Kazuhide Tomiyasu ,  Masao Moriguchi ,  Yutaka Takafuji

IPC分类号： H01L29/786 ,  H01L21/762

CPC分类号： H01L27/1266 ,  H01L21/76254 ,  H01L27/1214

摘要： A method for manufacturing a semiconductor device includes: a first step of forming a base layer, which includes an element portion having a gate electrode and a flat interlayer insulating film formed so as to cover the gate electrode; a second step of ion implanting a delamination material into the base layer to form a delamination layer; a third step of bonding the base layer to a substrate; and a fourth step of separating and removing a part of the base layer along the delamination layer. An implantation depth of the delamination material in the gate electrode is substantially the same as that of the delamination material in the interlayer insulating film.

摘要翻译： 一种制造半导体器件的方法包括：形成基底层的第一步骤，其包括具有栅电极的元件部分和形成为覆盖栅电极的平坦层间绝缘膜; 将分层材料离子注入基层以形成分层的第二步骤; 将基底层粘合到基底上的第三步骤; 以及沿剥离层分离除去基底层的一部分的第四工序。 栅电极中的分层材料的注入深度与层间绝缘膜中的分层材料的植入深度基本相同。

公开(公告)号：US07829400B2

公开(公告)日：2010-11-09

申请号：US11792487

申请日：2005-11-15

申请人： Yasumori Fukushima ,  Yutaka Takafuji ,  Masao Moriguchi

发明人： Yasumori Fukushima ,  Yutaka Takafuji ,  Masao Moriguchi

IPC分类号： H01L21/8234

CPC分类号： H01L27/1203 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/265 ,  H01L21/31662 ,  H01L21/32 ,  H01L21/76254 ,  H01L21/84 ,  H01L29/7833

摘要： In fabricating a semiconductor device, an element forming surface formation step of forming a plurality of element forming surfaces of different heights on a semiconductor layer to have different levels, a semiconductor element formation step of forming a plurality of semiconductor elements and, one in each of a corresponding number of regions of the semiconductor layer, each region including an associated one of the plurality of element forming surfaces, a level-difference compensation insulating film formation step of forming a level-difference compensation insulating film on the semiconductor layer to cover the semiconductor elements and have a surface with different levels along the element forming surfaces, a release layer formation step of forming a release layer in the semiconductor layer by ion-implanting a peeling material through the level-difference compensation insulating film into the semiconductor layer, and a separation step of separating part of the semiconductor layer along the release layer are performed.

摘要翻译： 在制造半导体器件时，在半导体层上形成具有不同高度的多个元件形成表面以形成不同电平的元件形成表面形成步骤，形成多个半导体元件的半导体元件形成步骤和 所述半导体层的相应数量的区域，每个区域包括所述多个元件形成表面中的相关联的一个元件形成表面;电平差补偿绝缘膜形成步骤，在所述半导体层上形成电平差补偿绝缘膜以覆盖所述半导体 元件，并且具有沿着元件形成表面具有不同水平的表面;剥离层形成步骤，通过将剥离材料通过电位差补偿绝缘膜离子注入到半导体层中而在半导体层中形成剥离层，以及 分离半导体层的一部分的分离步骤 沿着释放层进行。

公开(公告)号：US20080318390A1

公开(公告)日：2008-12-25

申请号：US12222598

申请日：2008-08-12

申请人： Yasumori Fukushima ,  Masao Moriguchi ,  Yutaka Takafuji

发明人： Yasumori Fukushima ,  Masao Moriguchi ,  Yutaka Takafuji

IPC分类号： H01L21/76

CPC分类号： H01L21/84 ,  H01L21/32 ,  H01L21/76254 ,  H01L27/1203 ,  H01L29/78654

摘要： A method for fabricating a semiconductor device according to the present invention is a method for fabricating a semiconductor device including a substrate layer including a plurality of first regions each having an active region and a plurality of second regions each being provided between adjacent ones of the first region. The fabrication method includes an isolation insulation film formation step of forming an isolation insulation film in each of the second regions so that a surface of the isolation insulation film becomes at the same height as that of a surface of a gate oxide film covering the active region, a peeling layer formation step of forming a peeling layer by ion-implanting hydrogen into the substrate layer after the isolation insulation film formation step, and a separation step of separating part of the substrate layer along the peeling layer.