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公开(公告)号：US09482417B2
公开(公告)日：2016-11-01
申请号：US13561475
申请日：2012-07-30
IPC分类号： B60Q1/44 , F21V21/34 , F21Y105/00
CPC分类号： F21V21/34 , F21Y2105/00 , F21Y2115/20
摘要： An illumination device includes a light emitting panel and a device body to which the light emitting panel is detachably attached. The light emitting panel has a rear surface serving as a first curved surface. The device body has a surface serving as a second curved surface conforming to the first curved surface. An attachment portion for attaching/detaching the light emitting panel to/from the device body to slide along the first curved surface or the second curved surface is provided on one of the rear surface of the light emitting panel facing the device body and surface of the device body facing the light emitting panel. A groove portion for enabling the attachment portion to slide is provided on the other of the rear surface of the light emitting panel facing the device body and the surface of the device body facing the light emitting panel.
摘要翻译： 照明装置包括发光面板和发光面板可拆卸地附接到的装置主体。 发光面板具有用作第一曲面的后表面。 装置本体具有与第一曲面相符的第二曲面的表面。 用于将发光板连接/从装置主体滑动以沿着第一弯曲表面或第二弯曲表面滑动的附接部分设置在发光面板的面向装置主体和表面的一个后表面上 装置主体面向发光面板。 在面向装置主体的发光面板的后表面和与发光面板相对的装置主体的表面上的另一个面上设置有用于使安装部滑动的槽部。
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公开(公告)号：US08356446B2
公开(公告)日：2013-01-22
申请号：US12881874
申请日：2010-09-14
申请人： Masashi Takeda , Masakuni Takeda
发明人： Masashi Takeda , Masakuni Takeda
IPC分类号： E04H1/00
CPC分类号： E04H3/02 , A47C29/003 , A61G7/0526 , E04B1/3483 , E04B1/5825 , E04B1/5831 , E04B2001/405 , E04H1/125 , F16B7/187
摘要： A capsule room unit for use as a capsule bed or other private space has a horizontally oblong rectangular parallelepiped room framework formed by columns, beams and panel materials fitted into the room framework to constitute a ceiling, a floor and walls, wherein the columns and the beams are composed of extruded materials each having a longitudinally consecutive groove. The panel materials of the ceiling and walls are composed of synthetic resin or FRP hollow panel materials each having peripheral flanges at a periphery along a plane direction, and the flanges of the hollow panel material are inserted and fitted to the grooves of the extruded materials.
摘要翻译： 用作胶囊床或其他私人空间的胶囊室单元具有由柱，梁和面板材料形成的水平方形长方体的平行六面体框架，该框架安装在房间框架中以构成天花板，地板和墙壁，其中柱和 梁由挤压材料组成，各自具有纵向连续的凹槽。 天花板和墙壁的面板材料由合成树脂或FRP中空板材料组成，每个板材沿着平面方向在周边具有周边凸缘，并且中空板材料的凸缘插入并装配到挤压材料的槽中。
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公开(公告)号：US20120329303A1
公开(公告)日：2012-12-27
申请号：US13528296
申请日：2012-06-20
IPC分类号： H01R13/52
CPC分类号： H01R33/9658
摘要： A waterproof socket includes a socket body having an insertion hole to which a lamp pin protruding from an end cap of a straight tube lamp is inserted, a first internal sleeve making contact with the socket body, and a second internal sleeve. The socket body includes a body-side rotation restraint portion engaging with a sleeve-side rotation restraint portion formed in the first internal sleeve to restrain the first internal sleeve from rotating about a center axis of the straight tube lamp. The first internal sleeve includes a first position restraint portion and the second internal sleeve includes a second position restraint portion engaging with the first position restraint portion to restrain the second internal sleeve from rotating about the center axis while allowing the second internal sleeve to move in an axial direction of the straight tube lamp.
摘要翻译： 防水插座包括具有插入孔的插座主体，插入从直管灯的端盖突出的灯销，与插座主体接触的第一内部套筒和第二内部套筒。 插座主体包括与形成在第一内部套筒中的套筒侧旋转限制部接合的主体侧旋转限制部，以约束第一内部套筒围绕直管灯的中心轴线旋转。 第一内部套筒包括第一位置限制部分，并且第二内部套筒包括与第一位置限制部分接合的第二位置限制部分，以限制第二内部套筒围绕中心轴线旋转，同时允许第二内部套筒以 直管灯的轴向。
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公开(公告)号：US07222076B2
公开(公告)日：2007-05-22
申请号：US10276935
申请日：2002-03-22
申请人： Erika Kobayashi , Makoto Akabane , Tomoaki Nitta , Hideki Kishi , Rika Horinaka , Masashi Takeda
发明人： Erika Kobayashi , Makoto Akabane , Tomoaki Nitta , Hideki Kishi , Rika Horinaka , Masashi Takeda
IPC分类号： G10L15/00
CPC分类号： G10L13/033 , G10L13/00 , G10L2015/228
摘要： The present invention relates to a voice output apparatus capable of, in response to a particular stimulus, stopping outputting a voice and outputting a reaction. The voice output apparatus is capable of outputting a voice in a natural manner. A rule-based synthesizer 24 produces a synthesized voice and outputs it. For example, when a synthesized voice “Where is an exit” was produced and outputting of the synthesized voice data has proceeded until “Where is an e” has been output, if a user taps a robot, then a reaction generator 30 determines, by referring to a reaction database 31, that a reaction voice “Ouch!” should be output in response to being tapped. The reaction generator 30 then controls an output controller 27 so as to stop outputting the synthesized voice “Where is an exit?” and output the reaction voice “Ouch!”. Thereafter, the reaction generator 30 controls the read pointer of a buffer 26 controlled by the read controller 29 such that the outputting of the synthesized voice is resumed from the point at which the outputting was stopped. Thus, the synthesized voice “Where is an e, Ouch!, xit?” is output.
摘要翻译： 本发明涉及一种语音输出装置，其能够响应于特定的刺激，停止输出语音并输出反应。 语音输出装置能够以自然的方式输出声音。 基于规则的合成器24产生合成语音并输出它。 例如，当合成声音“出现在哪里”时，合成语音数据的输出已经进行到“输出了哪里”，如果用户点击机器人，则反应发生器30通过 指反应数据库31，反应声音“噢！” 应该被输出以响应被点击。 然后，反应发生器30控制输出控制器27，以便停止输出合成语音“出口在哪里”？ 并输出反应声音“哦！”。 此后，反应发生器30控制由读取控制器29控制的缓冲器26的读取指针，使得从输出停止的点恢复合成语音的输出。 因此，合成的声音“哪里是e，呃！xit？” 被输出。
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公开(公告)号：US6104626A
公开(公告)日：2000-08-15
申请号：US808866
申请日：1997-02-28
申请人： Masayuki Katakura , Masashi Takeda
发明人： Masayuki Katakura , Masashi Takeda
摘要： An analog delay circuit which includes an analog memory circuit wherein a plurality of memory cells each including a memory capacitor and a selection switch for the memory capacitor are arranged in a matrix includes row switches provided for the individual columns for individually being driven by row selection signals. A same clock signal from a clock generation circuit is supplied commonly to an X direction scanning circuit and a Y direction scanning circuit. The number of stages of registers of the X direction scanning circuit and the number of stages of registers of the Y direction scanning circuit are set so that they have no common divisor other than 1 Consequently, when the memory cells are to be selectively scanned, a same selection condition can be provided to all of the memory cells without relying upon the positions of the memory cells, and the parasitic capacitance connected to a signal write/read terminal is reduced.
摘要翻译： 一种包括模拟存储电路的模拟延迟电路，其中包括存储电容器和用于存储电容器的选择开关的多个存储单元被布置成矩阵，包括为各个列提供的行开关，用于单独由行选择信号驱动 。 来自时钟发生电路的相同时钟信号被共同地提供给X方向扫描电路和Y方向扫描电路。 X方向扫描电路的寄存器的级数和Y方向扫描电路的寄存器的级数被设置为使得它们除了1之外没有公共除数。因此，当要选择性地扫描存储器单元时， 可以在不依赖于存储单元的位置的情况下，向所有存储单元提供相同的选择条件，并且减少连接到信号写入/读取端子的寄生电容。
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公开(公告)号：US5510654A
公开(公告)日：1996-04-23
申请号：US460643
申请日：1995-06-02
申请人： Tomoki Nishino , Masashi Takeda
发明人： Tomoki Nishino , Masashi Takeda
IPC分类号： H01L21/822 , H01L21/60 , H01L23/485 , H01L23/528 , H01L27/04 , H01L23/48
CPC分类号： H01L24/50 , H01L23/528 , H01L24/05 , H01L24/06 , H01L24/48 , H01L24/86 , H01L2224/02166 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05556 , H01L2224/05599 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48599 , H01L24/45 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/1433 , H01L2924/20753
摘要： A semiconductor device having any arbitrary size. The number of input/output terminals can be easily and selectively increased while using input/output amplifier circuit functional portions having the same circuit configuration, by using both ball bonding and TAB bonding techniques. Every two (4A, 4B) of the electrodes on the semiconductor device correspond to each one set of input/output amplifier circuits formed by three ones (6A, 6B, 6C) of the input/output amplifier circuits. The spacing S.sub.1 between the two electrodes (4A, 4B) corresponding to one set of input/output amplifier circuits is substantially equal to the spacing S.sub.2 between the electrode 4B and the adjacent electrode 4C of one adjacent set of input/output amplifier circuits and also to the spacing S.sub.3 between the electrode 4A and the adjacent electrode 4D of the other adjacent set of input/output amplifier circuits.
摘要翻译： 具有任意尺寸的半导体器件。 使用具有相同电路结构的输入/输出放大器电路功能部分，通过使用滚珠接合和TAB接合技术，可以容易且有选择地增加输入/输出端子的数量。 半导体器件上的每两个电极（4A，4B）对应于由输入/输出放大器电路的三个（6A，6B，6C）形成的每组输入/输出放大器电路。 对应于一组输入/输出放大器电路的两个电极（4A，4B）之间的间隔S1基本上等于一组相邻输入/输出放大器电路的电极4B和相邻电极4C之间的间隔S2， 相对于另一相邻输入/输出放大器电路组的电极4A和相邻电极4D之间的间隔S3。
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公开(公告)号：US4568910A
公开(公告)日：1986-02-04
申请号：US450777
申请日：1982-12-17
申请人： Takeo Sekino , Masashi Takeda
发明人： Takeo Sekino , Masashi Takeda
CPC分类号： H03M1/361
摘要： An analog-to-digital converter for converting an analog input signal to a digital output signal with m upper bits and n lower bits includes 2.sup.m+n -1 resistors establishing 2.sup.m+n reference voltages for comparison with an amplitude of the analog input signal, 2.sup.m -1 voltage comparing circuits for comparing the analog input signal with 2.sup.n step-by-step reference voltages, a first encoder for encoding the output signals of the 2.sup.m-1 voltage comparing circuits for generating m upper bits of the digital output signal, a matrix circuit having 2.sup.m (2.sup.n -1) voltage comparators for comparing the analog input signal with the remaining reference voltages of the 2.sup.m+n references voltages, the other voltage comparing circuits being supplied output signals of the matrix circuit and a second encoder for encoding output signals of the other voltage comparing circuits for generating n lower bits of the digital output signal.
摘要翻译： 用于将模拟输入信号转换为具有m个高位和n个低位的数字输出信号的模数转换器包括建立2m + n个参考电压的2m + n-1个电阻器，用于与模拟输入信号的幅度进行比较， 用于将模拟输入信号与2n个逐步参考电压进行比较的2m-1个电压比较电路，用于对2m-1个电压比较电路的输出信号进行编码以产生数字输出信号的m个高位的第一编码器， 具有2m（2n-1）个电压比较器的矩阵电路，用于将模拟输入信号与2m + n个参考电压的剩余参考电压进行比较，其他电压比较电路是矩阵电路的输出信号和用于编码输出的第二编码器 用于产生数字输出信号的n个较低位的其它电压比较电路的信号。
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公开(公告)号：US4539553A
公开(公告)日：1985-09-03
申请号：US480078
申请日：1983-03-29
申请人： Masashi Takeda , Masaru Iwasa
发明人： Masashi Takeda , Masaru Iwasa
CPC分类号： H03M1/74
摘要： A digital-to-analog converter of the current-adding kind includes n input buffer circuits to which the bits of the digital signal are applied in parallel, a first ladder resistor network having n resistors connected in series to which complementary outputs of the input buffer circuit are connected, a second ladder resistor network for dividing output terminal voltages from the first ladder resistor network into 2(2.sup.n -1) voltages, (2.sup.n -1) switching circuits having inputs connected to voltage dividing points of the second resistor network, and a common summing resistor connected to the outputs of the switching circuits to add currents supplied thereto, thereby providing an analog voltage having a level corresponding to the numerical value of the digital input signal.
摘要翻译： 电流相加型的数模转换器包括并行施加数字信号的位的n个输入缓冲电路，具有串联连接的n个电阻器的第一梯形电阻器网络，输入缓冲器的互补输出 电路连接，用于将来自第一梯形电阻网络的输出端电压分为2（2n-1）个电压的第二梯形电阻网络，具有连接到第二电阻网络的分压点的输入的（2n-1）个开关电路，以及 连接到开关电路的输出的公共求和电阻器，以增加提供给其的电流，从而提供具有与数字输入信号的数值对应的电平的模拟电压。
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公开(公告)号：US4514787A
公开(公告)日：1985-04-30
申请号：US491885
申请日：1983-05-05
申请人： Fumihiko Kaneko , Tetsuya Murakawa , Koichi Nitta , Noriaki Yamana , Masashi Takeda , Kunio Tachi
发明人： Fumihiko Kaneko , Tetsuya Murakawa , Koichi Nitta , Noriaki Yamana , Masashi Takeda , Kunio Tachi
CPC分类号： H05K13/003
摘要： An electronic component series wherein a plurality of parallel lead type electronic components (1) each having two parallel lead wires (4) are equispaced along a retainer band (2) and distributed along the length of the retainer band (2) with the lead wires (4) extending in the same direction and are positioned by the retainer band (2), whereby the electronic components (1) are retained. The electronic component series is characterized in that the distance (A) between the pair of lead wires (4) of each electronic component (1) in a region (4a) where the lead wires (4) are placed on the retainer band (2) is made different from that (B) in a region (4c) closer to the electronic component main body (3), while the intermediate portions (4b) of the lead wires (4) are bent to absorb the difference in dimension between the distances (A, B).
摘要翻译： 一种电子部件系列，其中，具有两个平行的引线（4）的多个平行的引线型电子部件（1）沿着保持器带（2）等距并沿着所述保持器带（2）的长度分布，所述引线 （4）沿相同的方向延伸并且由保持器带（2）定位，由此保持电子部件（1）。 电子部件系列的特征在于，在引线（4）放置在保持带（2）上的区域（4a）中的每个电子部件（1）的一对引线（4）之间的距离（A） ）在靠近电子部件主体（3）的区域（4c）中与（B）不同，而引线（4）的中间部分（4b）被弯曲以吸收彼此之间的尺寸差异 距离（A，B）。
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公开(公告)号：US4352027A
公开(公告)日：1982-09-28
申请号：US156209
申请日：1980-06-03
申请人： Masayuki Miyake , Takeo Sekino , Masashi Takeda
发明人： Masayuki Miyake , Takeo Sekino , Masashi Takeda
CPC分类号： H01L27/0233 , G11C19/28
摘要： A shift register having a plurality of flip-flop circuits connected in cascade in which a clock pulse is supplied to the flip-flop circuit at the final stage and the AND-outputs from the respective stage of flip-flop circuits are supplied to the preceding stage of flip-flop circuits as clock pulses, whereby the input data are shifted or transferred in synchronism with the clock pulse.
摘要翻译： 具有串联连接的多个触发电路的移位寄存器，其中在最后级将时钟脉冲提供给触发器电路，并且将来自触发器电路的各级的AND输出提供给前一个 触发器电路的级作为时钟脉冲，由此输入数据与时钟脉冲同步地移位或传送。
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