公开(公告)号：US20090290444A1

公开(公告)日：2009-11-26

申请号：US12094768

申请日：2005-11-28

申请人： Masayuki Satoh

发明人： Masayuki Satoh

IPC分类号： G11C8/00 ,  G11C7/00

CPC分类号： H03K19/1776 ,  H03K19/17728

摘要： A semiconductor device includes a plurality of memory cell blocks, each including a plurality of memory cells each storing a predetermined amount of data. Each of the memory cell blocks stores, in the memory cells thereof, truth table data used for outputting desired logical values in response to input of a given address so as to function as a logic circuit. The number of inputs and the number of outputs of the memory cell block is three or more, and the memory cell blocks are connected to each other so that three or more outputs from one memory cell block are input to three or more other memory cell blocks.

摘要翻译： 半导体器件包括多个存储单元块，每个存储单元块包括多个存储单元，每个存储单元存储预定量的数据。 每个存储器单元块在其存储单元中存储用于响应于给定地址的输入而输出所需逻辑值以用作逻辑电路的真值表数据。 存储单元块的输入数量和输出数量为三个以上，并且存储单元块彼此连接，使得来自一个存储器单元块的三个或更多个输出被输入到三个或更多个其他存储单元块 。

公开(公告)号：US20090154282A1

公开(公告)日：2009-06-18

申请号：US12094770

申请日：2006-07-06

申请人： Masayuki Satoh

发明人： Masayuki Satoh

IPC分类号： G11C8/00

CPC分类号： H03K19/1776 ,  H03K19/17728

摘要： A semiconductor device comprises multiple memory cell blocks including multiple memory cells for storing a predetermined amount of data. Each of the memory cell blocks having three or more inputs and three or more outputs includes two readout address decoders as to the memory cells internally, stores truth table data for outputting a desired logical value as to predetermined address input, and is configured so as to operate as a logic circuit. Also, the memory cells include two readout word lines corresponding to the two readout address decoders, and in the case of the voltage of both of the two readout word lines being applied, the data held at this time is read out from readout data lines. Further, between the memory cell blocks is connected such that the three or more outputs from one memory cell block are input to three or more other memory cell blocks.

摘要翻译： 半导体器件包括多个存储器单元块，其包括用于存储预定量的数据的多个存储器单元。 具有三个或更多个输入和三个或更多个输出的每个存储单元块包括两个内部存储单元的读出地址解码器，存储用于输出关于预定地址输入的期望逻辑值的真值表数据，并且被配置为 作为逻辑电路运行。 此外，存储单元包括对应于两个读出地址解码器的两个读出字线，并且在施加两个读出字线的电压的情况下，从读出数据线读出此时保持的数据。 此外，在存储单元块之间连接使得来自一个存储器单元块的三个或更多个输出被输入到三个或更多个其他存储单元块。

公开(公告)号：US08050132B2

公开(公告)日：2011-11-01

申请号：US12666251

申请日：2007-06-25

申请人： Masayuki Satoh

发明人： Masayuki Satoh

IPC分类号： G11C8/00

CPC分类号： H03K19/1776 ,  G01R31/318511 ,  G01R31/318516 ,  G11C29/56 ,  H03K19/17728 ,  H03K19/17736

摘要： A semiconductor device 110 has a plurality of memory cell blocks provided with a plurality of memory cells storing a predetermined amount of data. Each memory cell block has four or more inputs and outputs, and is internally provided with a read address decoder to the memory cell and a sense amplifier for amplifying a voltage in outputting outside. Each memory cell block is structured so as to store a truth table data for outputting a desired logic value in response to a specified address input, thereby operating as a logic circuit. The memory cell has a read word line correspondingly to the read address decoder. In the case when a voltage is applied to the read word line, the data that is held at that time is read from a read data line. The memory cell blocks are connected to each other such that the four or more outputs from one memory cell block are inputted to other four or more memory cell blocks through the sense amplifier.

摘要翻译： 半导体器件110具有设置有存储预定量的数据的多个存储单元的多个存储单元块。 每个存储器单元块具有四个或更多个输入和输出，并且在内部设置有读取地址解码器到存储单元，以及读出放大器，用于放大输出外部的电压。 每个存储器单元块被构造为存储用于响应于指定地址输入而输出期望逻辑值的真值表数据，从而作为逻辑电路工作。 存储单元具有对应于读地址解码器的读字线。 在对读取的字线施加电压的情况下，从读取数据线读出该时刻保持的数据。 存储单元块彼此连接，使得来自一个存储器单元块的四个或更多个输出通过读出放大器输入到其他四个或更多个存储单元块。

公开(公告)号：US20100188923A1

公开(公告)日：2010-07-29

申请号：US12666251

申请日：2007-06-25

申请人： Masayuki Satoh

发明人： Masayuki Satoh

IPC分类号： G11C8/00

CPC分类号： H03K19/1776 ,  G01R31/318511 ,  G01R31/318516 ,  G11C29/56 ,  H03K19/17728 ,  H03K19/17736

摘要： A semiconductor device 110 has a plurality of memory cell blocks provided with a plurality of memory cells storing a predetermined amount of data. Each memory cell block has four or more inputs and outputs, and is internally provided with a read address decoder to the memory cell and a sense amplifier for amplifying a voltage in outputting outside. Each memory cell block is structured so as to store a truth table data for outputting a desired logic value in response to a specified address input, thereby operating as a logic circuit. The memory cell has a read word line correspondingly to the read address decoder. In the case when a voltage is applied to the read word line, the data that is held at that time is read from a read data line. The memory cell blocks are connected to each other such that the four or more outputs from one memory cell block are inputted to other four or more memory cell blocks through the sense amplifier.

摘要翻译： 半导体器件110具有设置有存储预定量的数据的多个存储单元的多个存储单元块。 每个存储器单元块具有四个或更多个输入和输出，并且在内部设置有读取地址解码器到存储单元，以及读出放大器，用于放大输出外部的电压。 每个存储器单元块被构造为存储用于响应于指定地址输入而输出期望逻辑值的真值表数据，从而作为逻辑电路工作。 存储单元具有对应于读地址解码器的读字线。 在对读取的字线施加电压的情况下，从读取数据线读出该时刻保持的数据。 存储单元块彼此连接，使得来自一个存储器单元块的四个或更多个输出通过读出放大器输入到其他四个或更多个存储单元块。

公开(公告)号：US20100065846A1

公开(公告)日：2010-03-18

申请号：US12092238

申请日：2005-11-02

申请人： Masayuki SATOH

发明人： Masayuki SATOH

IPC分类号： H01L23/544

CPC分类号： G01R31/2818 ,  G01R31/2884 ,  G01R31/318533 ,  G11C29/40 ,  G11C29/48 ,  G11C29/56 ,  G11C2029/0401 ,  G11C2029/3202 ,  G11C2029/5602 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/13091 ,  H01L2924/15192 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2224/0401

摘要： This invention relates to a system in package including a plurality of integrated circuit chips and a substrate on which the plurality of integrated circuit chips are mounted and characterized in that a testability circuit for facilitating a test on at least one of the integrated circuit chips is incorporated into the substrate. The testability circuit incorporated into the substrate is formed by embedding a so-called WLCSP integrated circuit chip into the substrate. Alternatively, the testability circuit is formed by using a transistor element formed by using a semiconductor layer formed on the substrate. By incorporating the testability circuit into the substrate as described above, it is possible to realize a system in package facilitated in test without increases in size and cost.

摘要翻译： 本发明涉及包括多个集成电路芯片的多个集成电路芯片和其上安装有多个集成电路芯片的基板的系统，其特征在于，包括用于促进至少一个集成电路芯片的测试的可测试性电路 进入基板。 通过将所谓的WLCSP集成电路芯片嵌入到基板中来形成结合到基板中的可测试性电路。 或者，通过使用通过使用形成在基板上的半导体层形成的晶体管元件来形成可测试性电路。 通过将可测试性电路并入到基板中，可以在不增加尺寸和成本的情况下实现测试中促进的封装体系。

公开(公告)号：US07892975B2

公开(公告)日：2011-02-22

申请号：US11688684

申请日：2007-03-20

申请人： Eiichi Kondoh ,  Michiru Hirose ,  Hitoshi Tanaka ,  Masayuki Satoh ,  Hisashi Yano ,  Masaki Yoshimaru

发明人： Eiichi Kondoh ,  Michiru Hirose ,  Hitoshi Tanaka ,  Masayuki Satoh ,  Hisashi Yano ,  Masaki Yoshimaru

IPC分类号： H01L21/441

CPC分类号： H01L21/76879 ,  C23C18/1216 ,  C23C18/1279 ,  C23C18/1283 ,  H01L21/288 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for selectively forming an electric conductor, the method including disposing a processing target and a metal compound in an atmosphere including a supercritical fluid, the processing target having formed thereon at least one recess for providing an electric conductor, the metal compound including a metal serving as a main component of the electric conductor, and dissolving at least part of the metal compound in the supercritical fluid, selectively introducing the metal compound dissolved in the supercritical fluid into the recess in contact with a surface of the processing target, and coagulating in the recess the metal compound introduced into the recess to precipitate the metal from the metal compound, and coagulating the metal precipitated in the recess, thereby providing the electric conductor in the recess.

摘要翻译： 一种用于选择性地形成电导体的方法，所述方法包括在包括超临界流体的气氛中设置处理对象和金属化合物，所述处理对象在其上形成有至少一个用于提供导电体的凹部，所述金属化合物包括金属 作为电导体的主要成分，将至少一部分金属化合物溶解在超临界流体中，选择性地将溶解在超临界流体中的金属化合物导入到与加工对象的表面接触的凹部中， 所述金属化合物引入所述凹部中以将所述金属从所述金属化合物中沉淀出来并将所述金属凝结在所述凹部中沉淀，由此在所述凹部中提供所述电导体。

公开(公告)号：US20080206949A1

公开(公告)日：2008-08-28

申请号：US11845615

申请日：2007-08-27

申请人： Eiichi Kondoh ,  Michiru Hirose ,  Hitoshi Tanaka ,  Masayuki Satoh ,  Hisashi Yano ,  Masaki Yoshimaru

发明人： Eiichi Kondoh ,  Michiru Hirose ,  Hitoshi Tanaka ,  Masayuki Satoh ,  Hisashi Yano ,  Masaki Yoshimaru

IPC分类号： H01L21/44 ,  B05C11/00

CPC分类号： H01L21/283 ,  C23C18/06 ,  C23C18/08 ,  H01L21/76879

摘要： A conductor forming apparatus includes a reaction container having housed therein a processing target on a surface of which a recess in which a conductor is to be provided is formed, and a process for providing the conductor in the recess being carried out inside the container after a supercritical fluid dissolved with a metal compound is supplied into the container, a supply device which supplies the fluid from an outside to the inside of the container, and a discharge device which discharges the fluid that is not submitted for the process from the inside to the outside of the container, wherein while an amount of the fluid in the container is adjusted by continuously supplying the fluid into the container by the supply device and continuously discharging the fluid that is not submitted for the process to the outside of the container by the discharge device.

摘要翻译： 导体形成装置包括反应容器，其中容纳有处理目标，其表面上形成有要在其中设置导体的凹部，并且在凹部中提供导体的过程在容器内部被执行 将与金属化合物一起溶解的超临界流体供给到容器内，从外部向容器内部供给流体的供给装置以及将未从内部排出的流体从内部排出到 在容器外部，其中通过由供应装置连续地将流体供给到容器中并且通过排出物将不被处理的流体连续排出到容器的外部来调节容器中的流体的量 设备。

公开(公告)号：US08253238B2

公开(公告)日：2012-08-28

申请号：US12882896

申请日：2010-09-15

申请人： Masayuki Satoh ,  Koshi Maemura

发明人： Masayuki Satoh ,  Koshi Maemura

IPC分类号： H01L23/48 ,  H01L21/00

CPC分类号： H01L21/565 ,  H01L21/4842 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4912 ,  H01L2224/49171 ,  H01L2224/78301 ,  H01L2224/85181 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： In a resin-sealed semiconductor device, an inner lead including a bend portion formed by lifting has a protruding shape located on one side and an inclined vertical surface shape located on the other side (inside) in an external connection terminal direction. A cutaway portion is provided along the bend portion and an external connection terminal. A height of an upper surface portion of the inner lead is higher than a height of an upper surface of a semiconductor element. The inner lead is provided in a substantially central portion of a die pad so that the inclined vertical surface shape is parallel to a side of a die pad which includes a thin portion located in a side surface portion and an exposure portion located on a bottom surface.

摘要翻译： 在树脂密封型半导体装置中，包括由提升形成的弯曲部的内部引线在外部连接端子方向上具有位于一侧的突出形状和位于另一侧（内侧）的倾斜的垂直面形状。 沿弯曲部分设置切口部分和外部连接端子。 内引线的上表面部分的高度高于半导体元件的上表面的高度。 内引线设置在管芯焊盘的大致中央部分，使得倾斜的垂直表面形状平行于管芯焊盘的侧面，其包括位于侧表面部分中的薄部分和位于底表面上的暴露部分 。

公开(公告)号：US20100112776A1

公开(公告)日：2010-05-06

申请号：US12685408

申请日：2010-01-11

申请人： Eiichi Kondoh ,  Michiru Hirose ,  Hitoshi Tanaka ,  Masayuki Satoh ,  Hisashi Yano ,  Masaki Yoshimaru

发明人： Eiichi Kondoh ,  Michiru Hirose ,  Hitoshi Tanaka ,  Masayuki Satoh ,  Hisashi Yano ,  Masaki Yoshimaru

IPC分类号： H01L21/02 ,  B05D5/12

CPC分类号： H01L21/283 ,  C23C18/06 ,  C23C18/08 ,  H01L21/76879

摘要： A conductor forming apparatus includes a reaction container having housed therein a processing target on a surface of which a recess in which a conductor is to be provided is formed, and a process for providing the conductor in the recess being carried out inside the container after a supercritical fluid dissolved with a metal compound is supplied into the container, a supply device which supplies the fluid from an outside to the inside of the container, and a discharge device which discharges the fluid that is not submitted for the process from the inside to the outside of the container, wherein while an amount of the fluid in the container is adjusted by continuously supplying the fluid into the container by the supply device and continuously discharging the fluid that is not submitted for the process to the outside of the container by the discharge device.

摘要翻译： 导体形成装置包括反应容器，其中容纳有处理目标，其表面上形成有要在其中设置导体的凹部，并且在凹部中提供导体的过程在容器内部被执行 将与金属化合物一起溶解的超临界流体供给到容器内，从外部向容器内部供给流体的供给装置以及将未从内部排出的流体从内部排出到 在容器外部，其中通过由供应装置连续地将流体供给到容器中并且通过排出物将不被处理的流体连续排出到容器的外部来调节容器中的流体的量 设备。

公开(公告)号：US07652946B2

公开(公告)日：2010-01-26

申请号：US12094770

申请日：2006-07-06

申请人： Masayuki Satoh

发明人： Masayuki Satoh

IPC分类号： G11C8/00

CPC分类号： H03K19/1776 ,  H03K19/17728

摘要： A semiconductor device comprises multiple memory cell blocks including multiple memory cells for storing a predetermined amount of data. Each of the memory cell blocks having three or more inputs and three or more outputs includes two readout address decoders as to the memory cells internally, stores truth table data for outputting a desired logical value as to predetermined address input, and is configured so as to operate as a logic circuit. Also, the memory cells include two readout word lines corresponding to the two readout address decoders, and in the case of the voltage of both of the two readout word lines being applied, the data held at this time is read out from readout data lines. Further, between the memory cell blocks is connected such that the three or more outputs from one memory cell block are input to three or more other memory cell blocks.

摘要翻译： 半导体器件包括多个存储器单元块，其包括用于存储预定量的数据的多个存储器单元。 具有三个或更多个输入和三个或更多个输出的每个存储单元块包括两个内部存储单元的读出地址解码器，存储用于输出关于预定地址输入的期望逻辑值的真值表数据，并且被配置为 作为逻辑电路运行。 此外，存储单元包括对应于两个读出地址解码器的两个读出字线，并且在施加两个读出字线的电压的情况下，从读出数据线读出此时保持的数据。 此外，在存储单元块之间连接使得来自一个存储器单元块的三个或更多个输出被输入到三个或更多个其他存储单元块。