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公开(公告)号：US20150131384A1
公开(公告)日：2015-05-14
申请号：US14400500
申请日：2012-08-29
申请人： Tomoya Ogawa , Takashi Ito , Mitsuhiro Tomoeda
发明人： Tomoya Ogawa , Takashi Ito , Mitsuhiro Tomoeda
IPC分类号： G11C16/14
摘要： In a nonvolatile memory device (4) provided in a semiconductor device, when data is erased based on a band-to-band tunneling scheme, supply of a boosted voltage to a memory cell (MC) to be erased is ended when a condition that an output voltage (VUCP) of a charge pump circuit (52) has recovered to a predetermined reference voltage is satisfied and additionally a condition that a predetermined reference time has elapsed since start of supply of the boosted voltage (VUCP) to the memory cell (MC) to be erased is satisfied.
摘要翻译： 在设置在半导体器件中的非易失性存储器件（4）中，当基于带 - 带隧穿方案擦除数据时，在被擦除的存储器单元（MC）中提供升压电压将在 已经恢复到预定参考电压的电荷泵电路（52）的输出电压（VUCP）被满足，并且另外还有一个从提升升压电压（VUCP）开始到存储单元（VUCP）开始经过了预定基准时间的条件 MC）被清除。
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2.发明授权Flash memory having data refresh function and data refresh method of flash memory 失效闪存具有闪存的数据刷新功能和数据刷新方法
公开(公告)号：US5574684A
公开(公告)日：1996-11-12
申请号：US463802
申请日：1995-06-05
申请人： Mitsuhiro Tomoeda
发明人： Mitsuhiro Tomoeda
IPC分类号： G11C17/00 , G11C16/02 , G11C16/10 , G11C16/34 , G11C29/00 , G11C29/12 , G11C29/52 , G11C7/00
CPC分类号： G11C16/3431 , G11C16/10 , G11C16/3418 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C29/52
摘要： A flash memory and its data refresh method, where data read out in program verify mode and erase verify mode from read address are compared in each address (ST110), and data of a memory cell corresponding to inconsistent data are rewritten (ST112). Or adding values of data read out in the program verify mode and the erase verify mode are compared in each block (ST137) and a defective block is retrieved and data in each address are compared in the defective block (ST160), and data of a memory cell corresponding to inconsistent data are rewritten (ST162). Thereby, defective data can be retrieved and corrected.
摘要翻译： 在每个地址（ST110）中比较了闪存及其数据刷新方法，其中在每个地址（ST110）中比较从程序验证模式读出数据和擦除验证模式的数据刷新方法，并重写与不一致数据对应的存储单元的数据（ST112）。 或者在每个块（ST137）中比较在程序验证模式和擦除验证模式中读出的数据的值，并且在缺陷块（ST160）中比较缺陷块并比较每个地址中的数据，并且将数据 对应于不一致数据的存储单元被重写（ST162）。 从而可以检索和纠正有缺陷的数据。
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公开(公告)号：US08242808B2
公开(公告)日：2012-08-14
申请号：US13106573
申请日：2011-05-12
IPC分类号： G11C8/00 , H03K19/082 , H03K19/094
摘要： A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal.
摘要翻译： 获得正常可操作的解码器电路，而不需要解码操作的延迟，电路面积的增加和电路设计成本的增加。 高电压电路部分中的NMOS晶体管插在NAND门与节点的输出端之间，并在其栅电极处接收输入信号。 高压电路部分中的负载电流产生部分包括串联耦合在高电源电压和节点之间的PMOS晶体管。 一个PMOS晶体管在其栅电极处接收控制信号。 另一个PMOS晶体管在其栅电极处接收控制信号。 逆变器接收从节点获得的信号作为输入信号，并将其反相信号作为输出信号输出。
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公开(公告)号：US20110216620A1
公开(公告)日：2011-09-08
申请号：US13106573
申请日：2011-05-12
IPC分类号： G11C8/08
摘要： A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal.
摘要翻译： 获得正常可操作的解码器电路，而不需要解码操作的延迟，电路面积的增加和电路设计成本的增加。 高电压电路部分中的NMOS晶体管插在NAND门与节点的输出端之间，并在其栅电极处接收输入信号。 高压电路部分中的负载电流产生部分包括串联耦合在高电源电压和节点之间的PMOS晶体管。 一个PMOS晶体管在其栅电极处接收控制信号。 另一个PMOS晶体管在其栅电极处接收控制信号。 逆变器接收从节点获得的信号作为输入信号，并将其反相信号作为输出信号输出。
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公开(公告)号：US20050052908A1
公开(公告)日：2005-03-10
申请号：US10930806
申请日：2004-09-01
申请人： Mitsuhiro Tomoeda , Minoru Nakamura
发明人： Mitsuhiro Tomoeda , Minoru Nakamura
CPC分类号： G11C16/16
摘要： An operation of erasing data in a memory block of a nonvolatile semiconductor memory device employs an operation of collectively applying an erase pulse to the memory block, and an operation of collectively applying an erase pulse to a limited region in the memory block. Thereby, the number of the erase pulses excessively applied to the memory cells, which passed verify, can be reduced as compared with. a conventional structure so that the number of the memory cells to be subjected to over-erase recovery write decreases, and the total block erase time can be short.
摘要翻译： 擦除非易失性半导体存储器件的存储器块中的数据的操作采用对存储器块共同施加擦除脉冲的操作，以及对存储器块中的限制区域共同施加擦除脉冲的操作。 因此，与通过验证的过度地施加到存储单元的擦除脉冲的数量相比可以减少。 常规结构，使得要进行过擦除恢复写入的存储单元的数量减少，并且总块擦除时间可以较短。
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6.发明授权Nonvolatile semiconductor storage device having a shortened time required for a data erasing operation and data erasing method thereof 有权具有数据擦除操作所需时间缩短的数据擦除方法的非易失性半导体存储装置公开(公告)号：US06781882B2
公开(公告)日：2004-08-24
申请号：US10187981
申请日：2002-07-03
申请人： Satoshi Shimizu , Mitsuhiro Tomoeda
发明人： Satoshi Shimizu , Mitsuhiro Tomoeda
IPC分类号： G11C1604
CPC分类号： G11C16/3409 , G11C16/16 , G11C16/3404 , G11C16/344 , G11C16/3445
摘要： It is an object to obtain a nonvolatile semiconductor storage device and a data erasing method thereof in which a time required for a data erasing operation can be shortened. When second and succeeding erasing commands are input at a step SP101, a final voltage value of a batch writing pulse in a last data erasing operation is read from a storage portion (2a) at a step SP102. At a step SP103, next, a control portion (2) sets a starting voltage value of a batch writing pulse in a present data erasing operation based on the final voltage value of the batch writing pulse in the last data erasing operation. For example, in the case in which the final voltage value of the batch writing pulse in the last data erasing operation is VWL=8.00 V and VWell=VSL=−6.00 V, the starting voltage value of the batch writing pulse is currently set to VWL=7.75 V and VWell=VSL=−5.75 V with a reduction of one step.
摘要翻译： 本发明的目的是获得可以缩短数据擦除操作所需的时间的非易失性半导体存储装置及其数据擦除方法。 当在步骤SP101输入第二次和后续的擦除命令时，在步骤SP102从存储部分（2a）读取最后的数据擦除操作中批量写入脉冲的最终电压值。 在步骤SP103中，接下来，控制部分（2）在最后数据擦除操作中基于批量写入脉冲的最终电压值，在当前数据擦除操作中设置批量写入脉冲的起始电压值。 例如，在最后数据擦除操作中批量写入脉冲的最终电压值为VWL = 8.00V且VWell = VSL = -6.00V的情况下，批量写入脉冲的起始电压值当前被设定为 VWL = 7.75V，VWell = VSL = -5.75V，减少一步。
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公开(公告)号：US06515908B2
公开(公告)日：2003-02-04
申请号：US09845300
申请日：2001-05-01
IPC分类号： G11C1606
CPC分类号： G11C16/3409 , G11C16/16 , G11C16/3404 , G11C16/3445
摘要： Erasing is performed two times for narrowing a distribution width of threshold voltages of memory cells, and reducing the number of memory transistors to be subjected to over-erase verify. The erase verify voltage for the first erasing is set more strictly than the erase verify voltage for the second erasing. The erase pulses for the second erasing can be reduced in number, and the erasing time can be further reduced.
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8.发明授权公开(公告)号：US09177657B2
公开(公告)日：2015-11-03
申请号：US14400500
申请日：2012-08-29
申请人： Tomoya Ogawa , Takashi Ito , Mitsuhiro Tomoeda
发明人： Tomoya Ogawa , Takashi Ito , Mitsuhiro Tomoeda
摘要： In a nonvolatile memory device (4) provided in a semiconductor device, when data is erased based on a band-to-band tunneling scheme, supply of a boosted voltage to a memory cell (MC) to be erased is ended when a condition that an output voltage (VUCP) of a charge pump circuit (52) has recovered to a predetermined reference voltage is satisfied and additionally a condition that a predetermined reference time has elapsed since start of supply of the boosted voltage (VUCP) to the memory cell (MC) to be erased is satisfied.
摘要翻译： 在设置在半导体器件中的非易失性存储器件（4）中，当基于带 - 带隧穿方案擦除数据时，在被擦除的存储器单元（MC）中提供升压电压将在 已经恢复到预定参考电压的电荷泵电路（52）的输出电压（VUCP）被满足，并且另外还有一个从提升升压电压（VUCP）开始到存储单元（VUCP）开始经过了预定基准时间的条件 MC）被清除。
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公开(公告)号：US07969200B2
公开(公告)日：2011-06-28
申请号：US12845290
申请日：2010-07-28
IPC分类号： G11C8/00 , H03K19/082 , H03K19/094
摘要： A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal.
摘要翻译： 获得正常可操作的解码器电路，而不需要解码操作的延迟，电路面积的增加和电路设计成本的增加。 高电压电路部分中的NMOS晶体管插在NAND门与节点的输出端之间，并在其栅电极处接收输入信号。 高压电路部分中的负载电流产生部分包括串联耦合在高电源电压和节点之间的PMOS晶体管。 一个PMOS晶体管在其栅电极处接收控制信号。 另一个PMOS晶体管在其栅电极处接收控制信号。 逆变器接收从节点获得的信号作为输入信号，并将其反相信号作为输出信号输出。
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公开(公告)号：US20090237114A1
公开(公告)日：2009-09-24
申请号：US12361755
申请日：2009-01-29
IPC分类号： H03K19/00
摘要： A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal.
摘要翻译： 获得正常可操作的解码器电路，而不需要解码操作的延迟，电路面积的增加和电路设计成本的增加。 高电压电路部分中的NMOS晶体管插在NAND门与节点的输出端之间，并在其栅电极处接收输入信号。 高压电路部分中的负载电流产生部分包括串联耦合在高电源电压和节点之间的PMOS晶体管。 一个PMOS晶体管在其栅电极处接收控制信号。 另一个PMOS晶体管在其栅电极处接收控制信号。 逆变器接收从节点获得的信号作为输入信号，并将其反相信号作为输出信号输出。
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