公开(公告)号：US20100140711A1

公开(公告)日：2010-06-10

申请号：US12628364

申请日：2009-12-01

Applicant: Norio ISHITSUKA ,  Hiroyuki OHTA ,  Yasuhiro KIMURA ,  Natsuo YAMAGUCHI ,  Takashi TAKEUCHI ,  Shoji YOSHIDA

Inventor： Norio ISHITSUKA ,  Hiroyuki OHTA ,  Yasuhiro KIMURA ,  Natsuo YAMAGUCHI ,  Takashi TAKEUCHI ,  Shoji YOSHIDA

IPC: H01L27/12 ,  H01L21/86

CPC classification number: H01L21/26506 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823892 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/6659

Abstract: Generation of dislocation and increase of diffusion resistance at edge portions of source/drain regions in a CMIS are prevented. When source/drain regions in a CMIS are formed, argon is implanted to a P-well layer as a dislocation-suppressing element and nitrogen is implanted to an N-well layer as a dislocation-suppressing element before an ion implantation of impurities to a silicon substrate. In this manner, by separately implanting dislocation-suppressing elements suitable for each of the P-well layer and the N-well layer as well as suppressing the generation of dislocation, increase of diffusion resistance can be suppressed, yield can be improved, and the reliability of devices can be increased.

Abstract translation: 防止在CMIS中的源极/漏极区域的边缘部分产生位错并增加扩散电阻。 当形成CMIS中的源极/漏极区时，将氩作为位错抑制元素注入到P阱层中，并且在离子将杂质离子注入到N阱之前将氮注入作为位错抑制元素的N阱层 硅衬底。 以这种方式，通过分别植入适合于P阱层和N阱层中的每一个的位错抑制元件以及抑制位错的产生，可以抑制扩散电阻的增加，可以提高产率，并且 可以提高设备的可靠性。

公开(公告)号：US20050196935A1

公开(公告)日：2005-09-08

申请号：US11108827

申请日：2005-04-19

Applicant: Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasushi Matsuda ,  Yasuko Yoshida ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Akira Takamatsu ,  Hirofumi Shimizu ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

Inventor： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasushi Matsuda ,  Yasuko Yoshida ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Akira Takamatsu ,  Hirofumi Shimizu ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

IPC: H01L21/31 ,  H01L21/76 ,  H01L21/762

CPC classification number: H01L21/76232 ,  H01L21/76235 ,  H01L29/78

Abstract: A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.

公开(公告)号：US06881646B2

公开(公告)日：2005-04-19

申请号：US10392916

申请日：2003-03-21

Applicant: Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasushi Matsuda ,  Yasuko Yoshida ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Akira Takamatsu ,  Hirofumi Shimizu ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

Inventor： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasushi Matsuda ,  Yasuko Yoshida ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Akira Takamatsu ,  Hirofumi Shimizu ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

IPC: H01L21/31 ,  H01L21/76 ,  H01L21/762

CPC classification number: H01L21/76232 ,  H01L21/76235 ,  H01L29/78

Abstract: A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.

Abstract translation: 一种制造半导体器件的方法，该半导体器件具有高度可靠的凹槽隔离结构，其具有在凹槽上边缘处形成的所需曲率半径，并且不形成任何步骤。 通过减小半导体衬底上的元件隔离槽的槽上边缘周围的应力产生，从而优化元件隔离槽的形状并使器件更精细并提高器件电气特性来制造器件。

公开(公告)号：US20050079667A1

公开(公告)日：2005-04-14

申请号：US10503350

申请日：2003-02-05

Applicant: Tomio Iwasaki ,  Norio Ishitsuka ,  Hideo Miura

Inventor： Tomio Iwasaki ,  Norio Ishitsuka ,  Hideo Miura

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/8244 ,  H01L21/8247 ,  H01L27/11 ,  H01L27/115 ,  H01L29/49 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L21/425 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/76 ,  H01L29/94

CPC classification number: H01L29/6659 ,  H01L21/26513 ,  H01L29/4925 ,  H01L29/4983 ,  H01L29/7833

Abstract: A semiconductor device having a high degree of reliability is provided. A second object of the invention is to provide a semiconductor device of high yield. The semiconductor includes a silicon substrate, a gate dielectric film formed on one main surface of the silicon substrate, a gate electrode formed by being stacked on the gate dielectric film and a diffusion layer containing arsenic and phosphorus. Both of the concentration of the highest concentration portion of arsenic and the concentration of the highest concentration portion of phosphorus are each at 1026 atoms/m3 or more and 1027 atoms/m3 or less, and the depth of the highest concentration portion of phosphorus from the surface of the silicon substrate is less than the depth of the highest concentration portion of arsenic.

Abstract translation: 提供了具有高可靠性的半导体器件。 本发明的第二个目的是提供一种高产率的半导体器件。 半导体包括硅衬底，形成在硅衬底的一个主表面上的栅极电介质膜，通过层叠在栅极电介质膜上形成的栅电极和含有砷和磷的扩散层。 砷的最高浓度部分的浓度和磷的最高浓度部分的浓度分别为10 26个/ m 3以上且10 27个/ m 3以下， 并且来自硅衬底的表面的磷的最高浓度部分的深度小于砷的最高浓度部分的深度。

公开(公告)号：US06348396B1

公开(公告)日：2002-02-19

申请号：US09702786

申请日：2000-11-01

Applicant: Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida

Inventor： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida

IPC: H01L2176

CPC classification number: H01L21/76232

Abstract: A semiconductor device having a SGI structure produced by selecting D, T and R values for satisfying the formula: D

Abstract translation: 具有SGI结构的半导体器件通过选择满足下式的D，T和R值产生：其中D是元件形成区域的宽度，T是以微米为单位的槽的热氧化量，R是 在槽的端部底部的曲率半径具有优异的性能，例如在硅衬底中的凹槽底部产生的应力减小，并且不产生异常结漏电流。

公开(公告)号：US20140284753A1

公开(公告)日：2014-09-25

申请号：US14355104

申请日：2011-11-28

Applicant: Norio Ishitsuka ,  Keiji Hanzawa ,  Yasuo Onose ,  Noriyuki Sakuma

Inventor： Norio Ishitsuka ,  Keiji Hanzawa ,  Yasuo Onose ,  Noriyuki Sakuma

IPC: G01F1/69

CPC classification number: G01F1/69 ,  G01F1/692

Abstract: A thermal air flow sensor that produces less measurement error is provided. The thermal air flow sensor includes: a semiconductor substrate; a heating resistor, resistance temperature detectors, and an electrical insulator that includes a silicon oxide film, wherein the heating resistor, the resistance temperature detectors, and the electrical insulator are formed on the semiconductor substrate; and a diaphragm portion formed by removing a portion of the semiconductor substrate. The heating resistor and the resistance temperature detectors are formed on the diaphragm portion. The thermal air flow sensor further includes a silicon nitride film formed as the electrical insulator above the heating resistor and the resistance temperature detectors. The silicon nitride film has steps conforming to the patterns of the heating resistor and the resistance temperature detectors. The silicon nitride film has a multilayer structure.

Abstract translation: 提供了产生较少测量误差的热空气流量传感器。 热空气流量传感器包括：半导体衬底; 加热电阻器，电阻温度检测器和包括氧化硅膜的电绝缘体，其中在半导体衬底上形成有加热电阻器，电阻温度检测器和电绝缘体; 以及通过去除半导体衬底的一部分而形成的膜片部分。 加热电阻器和电阻温度检测器形成在隔膜部分上。 热空气流量传感器还包括形成为加热电阻器上方的电绝缘体的电阻温度检测器的氮化硅膜。 氮化硅膜具有符合加热电阻器和电阻温度检测器的图案的步骤。 氮化硅膜具有多层结构。

公开(公告)号：US08723287B2

公开(公告)日：2014-05-13

申请号：US13810814

申请日：2011-07-06

Applicant: Norio Ishitsuka ,  Rintaro Minamitani ,  Keiji Hanzawa

Inventor： Norio Ishitsuka ,  Rintaro Minamitani ,  Keiji Hanzawa

IPC: H01L31/058

CPC classification number: H01L37/00 ,  B81C1/00793 ,  G01F1/6845 ,  G01F1/692

Abstract: An object of the present invention is to provide a thermal airflow sensor that prevents moisture absorption by a silicon oxide film formed closest to a surface (formed to be located on an uppermost portion), and that reduces a measuring error. In order to attain the foregoing object, the thermal airflow sensor according to the present invention applies an ion implantation to a silicon oxide film 4, formed closest to a surface (formed to be located on an uppermost portion), by using an atom or molecule selected from at least any one of silicon, oxygen, and an inert element such as argon or nitrogen, in order to increase a concentration of an atom contained in the silicon oxide film 4 more than that before the ion implantation.

Abstract translation: 本发明的目的是提供一种热气流传感器，其防止由最靠近表面（形成在最上部的部分）形成的氧化硅膜吸湿，并且减少了测量误差。 为了实现上述目的，根据本发明的热气流传感器通过使用原子或分子将离子注入施加到最靠近表面（形成在最上部）的氧化硅膜4上 选自硅，氧和惰性元素如氩或氮中的至少一种，以便增加氧化硅膜4中包含的原子的浓度比离子注入之前的浓度更高。

公开(公告)号：US07674668B2

公开(公告)日：2010-03-09

申请号：US12005444

申请日：2007-12-26

Applicant: Norio Ishitsuka ,  Nobuyoshi Hattori ,  Tomio Iwasaki

Inventor： Norio Ishitsuka ,  Nobuyoshi Hattori ,  Tomio Iwasaki

IPC: H01L21/336 ,  H01L21/265

CPC classification number: H01L21/26506 ,  H01L21/26513 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

Abstract: After a gate electrode is formed on a main surface of a semiconductor substrate, low concentration layers are formed on the main surface of the semiconductor substrate by implanting impurities therein, with using the gate electrode as a mask. Thereafter, first sidewalls and second sidewalls are formed on the both side surfaces of the gate electrode. Subsequently, nitrogen or the like is ion-implanted into the semiconductor substrate, with using the first sidewalls, the second sidewalls and the gate electrode as a mask, thereby forming a crystallization-control region (CCR) on the main surface of the semiconductor substrate. Then, after the second sidewalls are removed, high concentration layers for a source and a drain are formed on the main surface of the semiconductor substrate.

Abstract translation: 在半导体衬底的主表面上形成栅电极之后，通过使用栅电极作为掩模，在半导体衬底的主表面上注入杂质，形成低浓度层。 此后，在栅电极的两个侧表面上形成第一侧壁和第二侧壁。 随后，使用第一侧壁，第二侧壁和栅电极作为掩模，将氮等离子注入到半导体衬底中，从而在半导体衬底的主表面上形成结晶化控制区域（CCR） 。 然后，在去除第二侧壁之后，在半导体衬底的主表面上形成用于源极和漏极的高浓度层。

公开(公告)号：US20090029524A1

公开(公告)日：2009-01-29

申请号：US12244621

申请日：2008-10-02

Applicant: Kenji KANAMITSU ,  Kouzou Watanabe ,  Norio Suzuki ,  Norio Ishitsuka

Inventor： Kenji KANAMITSU ,  Kouzou Watanabe ,  Norio Suzuki ,  Norio Ishitsuka

IPC: H01L21/762

CPC classification number: H01L21/823878 ,  H01L21/28061 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L29/4941 ,  H01L29/6659

Abstract: A semiconductor integrated circuit device and a method of manufacturing the same. The surface of a substrate of an active region surrounded by an element isolation trench is horizontally flat in the center portion of the active region but falls toward the side wall of the element isolation trench in the shoulder portion of the active region. This inclined surface contains two inclined surfaces having different inclination angles. The first inclined surface near the center portion of the active region is relatively steep and the second inclined surface near the side wall of the element isolation trench is gentler than the first inclined surface. The surface of the substrate in the shoulder portion of the active region is wholly rounded and has no angular portion.

Abstract translation: 一种半导体集成电路器件及其制造方法。 由元件隔离沟槽围绕的有源区的基板的表面在有源区的中心部分水平平坦，但是朝向有源区的肩部中的元件隔离沟的侧壁落下。 该倾斜面包含两个具有不同倾斜角的倾斜面。 有源区的中心部附近的第一倾斜面比较陡，元件隔离沟的侧壁附近的第二倾斜面比第一倾斜面更平缓。 有源区的肩部中的基板的表面完全是圆形的，并且没有角部。

公开(公告)号：US20060214254A1

公开(公告)日：2006-09-28

申请号：US11443226

申请日：2006-05-31

Applicant: Norio Ishitsuka ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Hideo Miura ,  Masahito Takahashi ,  Norio Suzuki ,  Shuji Ikeda ,  Hideki Tanaka ,  Hiroyuki Mima

Inventor： Norio Ishitsuka ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Hideo Miura ,  Masahito Takahashi ,  Norio Suzuki ,  Shuji Ikeda ,  Hideki Tanaka ,  Hiroyuki Mima

IPC: H01L29/00

CPC classification number: H01L27/11526 ,  H01L21/28123 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/105 ,  H01L27/11546

Abstract: To suppress occurrence of defects in a semiconductor substrate, a semiconductor device is constituted by having: the semiconductor substrate; an element isolating region having a trench formed in the semiconductor substrate and an embedding insulating film which is embedded into the trench; an active region formed adjacent to the element isolating region, in which a gate insulating film is formed and a gate electrode is formed on the gate insulating film; and a region formed in such a manner that at least a portion of the gate electrode is positioned on the element isolating region, and a first edge surface of an upper side of the embedding insulating film in a first element isolating region where the gate electrode is positioned is located above a second edge surface of the embedding insulating film in a second element isolating region where the gate electrode film is not positioned.

Abstract translation: 为了抑制半导体衬底中的缺陷的发生，半导体器件通过具有：半导体衬底; 具有形成在所述半导体衬底中的沟槽的元件隔离区域和嵌入所述沟槽中的嵌入绝缘膜; 形成在元件隔离区域附近形成的有源区，其中形成栅极绝缘膜并在栅极绝缘膜上形成栅电极; 以及形成为使得栅电极的至少一部分位于元件隔离区域上的区域，以及在栅电极为第一元件隔离区域的嵌入绝缘膜的上侧的第一边缘表面 定位在位于绝缘膜的第二边缘表面上方的第二元件隔离区域中，栅极电极膜未被定位。