公开(公告)号：US20180293701A1

公开(公告)日：2018-10-11

申请号：US15482680

申请日：2017-04-07

Applicant: ABHISHEK R. APPU ,  Joydeep Ray ,  Altug Koker ,  Balaji Vembu ,  Pattabhiraman K ,  Matthew B. Callaway

Inventor： ABHISHEK R. APPU ,  Joydeep Ray ,  Altug Koker ,  Balaji Vembu ,  Pattabhiraman K ,  Matthew B. Callaway

IPC: G06T1/60 ,  G06T15/00 ,  G06F9/455 ,  G06F9/50 ,  G06F9/48

CPC classification number: G06T1/60 ,  G06F9/45558 ,  G06F9/4881 ,  G06F9/5038 ,  G06F2009/45579 ,  G06F2009/45591 ,  G06T15/005

Abstract: An apparatus and method for dynamic provisioning, quality of service, and prioritization in a graphics processor. For example, one embodiment of an apparatus comprises a graphics processing unit (GPU) comprising a plurality of graphics processing resources; slice configuration hardware logic to logically subdivide the graphics processing resources into a plurality of slices; and slice allocation hardware logic to allocate a designated number of slices to each virtual machine (VM) of a plurality of VMs running in a virtualized execution environment, the slice allocation hardware logic to allocate different numbers of slices to different VMs based on graphics processing requirements and/or priorities of each of the VMs.

公开(公告)号：US20180300238A1

公开(公告)日：2018-10-18

申请号：US15488637

申请日：2017-04-17

Applicant: Balaji Vembu ,  Altug Koker ,  Josh B. Mastronarde ,  Nikos Kaburlasos ,  Abhishek R. Appu ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Subramaniam Maiyuran ,  Kiran C. Veernapu ,  Pattabhiraman K ,  Kamal Sinha ,  Bhushan M. Borole ,  Wenyin Fu ,  Joydeep Ray ,  Prasoonkumar Surti ,  Eric J. Hoekstra ,  Travis T. Schluessler ,  Linda L. Hurd

Inventor： Balaji Vembu ,  Altug Koker ,  Josh B. Mastronarde ,  Nikos Kaburlasos ,  Abhishek R. Appu ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Subramaniam Maiyuran ,  Kiran C. Veernapu ,  Pattabhiraman K ,  Kamal Sinha ,  Bhushan M. Borole ,  Wenyin Fu ,  Joydeep Ray ,  Prasoonkumar Surti ,  Eric J. Hoekstra ,  Travis T. Schluessler ,  Linda L. Hurd

IPC: G06F12/06

Abstract: Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to monitor cache utilization of an application during execution of the application for a workload; and a memory to store cache utilization statistics responsive to the monitored cache utilization. The processor is to determine an optimal cache configuration for the application based at least in part on the cache utilization statistics for the workload such that a smallest amount of cache is turned on for subsequent executions of the workload by the application.

公开(公告)号：US20220334982A1

公开(公告)日：2022-10-20

申请号：US17827556

申请日：2022-05-27

Applicant: NIRANJAN L. COORAY ,  ABHISHEK R. APPU ,  ALTUG KOKER ,  JOYDEEP RAY ,  BALAJI VEMBU ,  PATTABHIRAMAN K ,  DAVID PUFFER ,  DAVID J. COWPERTHWAITE ,  RAJESH M. SANKARAN ,  SATYESHWAR SINGH ,  SAMEER KP ,  ANKUR N. SHAH ,  KUN TIAN

Inventor： NIRANJAN L. COORAY ,  ABHISHEK R. APPU ,  ALTUG KOKER ,  JOYDEEP RAY ,  BALAJI VEMBU ,  PATTABHIRAMAN K ,  DAVID PUFFER ,  DAVID J. COWPERTHWAITE ,  RAJESH M. SANKARAN ,  SATYESHWAR SINGH ,  SAMEER KP ,  ANKUR N. SHAH ,  KUN TIAN

IPC: G06F13/16 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/0802 ,  G06F13/40

Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

公开(公告)号：US20180293185A1

公开(公告)日：2018-10-11

申请号：US15482666

申请日：2017-04-07

Applicant: BALAJI VEMBU ,  ALTUG KOKER ,  JOYDEEP RAY ,  ABHISHEK R. APPU ,  PATTABHIRAMAN K ,  NIRANJAN L. COORAY

Inventor： BALAJI VEMBU ,  ALTUG KOKER ,  JOYDEEP RAY ,  ABHISHEK R. APPU ,  PATTABHIRAMAN K ,  NIRANJAN L. COORAY

IPC: G06F13/16 ,  G06F3/06 ,  G06F12/0802 ,  G06F12/1045 ,  G06F13/40

Abstract: An apparatus and method for dynamic provisioning and traffic control on a memory fabric. For example, one embodiment of an apparatus comprises: a graphics processing unit (GPU) comprising a plurality of graphics processing resources; slice configuration hardware logic to logically subdivide the graphics processing resources into a plurality of slices; and slice allocation hardware logic to allocate a designated set of slices to each virtual machine (VM) of a plurality of VMs running in a virtualized execution environment; and a plurality of queues associated with each VM at different levels of a memory interconnection fabric, the queues for a first VM to store memory traffic for that VM at the different levels of the memory interconnection fabric; arbitration hardware logic coupled to the plurality of queues and distributed across the different levels of the memory interconnection fabric, the arbitration hardware logic to cause memory traffic to be blocked from one or more upstream queues of the first VM upon detecting that a downstream queue associated with the first VM is full or at a specified threshold.

公开(公告)号：US11768781B2

公开(公告)日：2023-09-26

申请号：US17827556

申请日：2022-05-27

Applicant: Niranjan L. Cooray ,  Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Balaji Vembu ,  Pattabhiraman K ,  David Puffer ,  David J. Cowperthwaite ,  Rajesh M. Sankaran ,  Satyeshwar Singh ,  Sameer Kp ,  Ankur N. Shah ,  Kun Tian

Inventor： Niranjan L. Cooray ,  Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Balaji Vembu ,  Pattabhiraman K ,  David Puffer ,  David J. Cowperthwaite ,  Rajesh M. Sankaran ,  Satyeshwar Singh ,  Sameer Kp ,  Ankur N. Shah ,  Kun Tian

IPC: G06F9/455 ,  G06F9/50 ,  G06F13/16 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/0802 ,  G06F13/40

CPC classification number: G06F13/16 ,  G06F12/0802 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F13/4068 ,  G06F2212/1024 ,  G06F2212/302 ,  G06F2212/60 ,  G06F2212/68

Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

公开(公告)号：US20190034326A1

公开(公告)日：2019-01-31

申请号：US15858704

申请日：2017-12-29

Applicant: HEMA CHAND NALLURI ,  BALAJI VEMBU ,  PATTABHIRAMAN K ,  ALTUG KOKER

Inventor： HEMA CHAND NALLURI ,  BALAJI VEMBU ,  PATTABHIRAMAN K ,  ALTUG KOKER

IPC: G06F12/02 ,  G06F12/12 ,  G06F13/26

Abstract: Graphics processing systems and methods are described. For example, one embodiment of a graphics processing apparatus comprises a graphics processing unit (GPU), the GPU including an on-die cache and a cache configuration circuitry to dynamically configure the on-die cache for a plurality of contexts executed by the GPU. The cache configuration block is to receive a cache configuration request, the cache configuration request including context-specific cache requirements for a new context, and determine a priority associated with the context-specific cache requirements. The CCB can compare the context-specific cache requirements with pre-existing cache requirements based on the priority, and reallocate the cache based on the context-specific cache requirements and the priority.

公开(公告)号：US20150100749A1

公开(公告)日：2015-04-09

申请号：US14045515

申请日：2013-10-03

Applicant: Altug Koker ,  JAYAKRISHNA P. S ,  Pattabhiraman K

Inventor： Altug Koker ,  JAYAKRISHNA P. S ,  Pattabhiraman K

IPC: G06F9/38

CPC classification number: G06F9/3826 ,  G06F9/3004 ,  G06F9/3834 ,  G06F12/0831 ,  Y02D10/13

Abstract: Methods and systems may provide for receiving a request to perform an atomic operation and adding the atomic operation to an execution pipeline of an arithmetic logic unit (ALU) for one or more pending atomic operations if the one or more pending atomic operations are associated with a memory location identified in the request. Additionally, at least a portion of the execution pipeline may bypass the memory location. In one example, adding the atomic operation to the execution pipeline includes populating a linked list with a modification associated with the atomic operation, wherein the linked list is dedicated to the memory location.

Abstract translation: 方法和系统可以提供用于接收执行原子操作的请求并将原子操作添加到用于一个或多个未决原子操作的算术逻辑单元（ALU）的执行流水线，如果所述一个或多个挂起的原子操作与 在请求中识别的内存位置。 另外，执行流水线的至少一部分可以绕过存储器位置。 在一个示例中，将原子操作添加到执行流水线包括用与原子操作相关联的修改来填充链接列表，其中链接列表专用于存储器位置。