公开(公告)号：US08492883B2

公开(公告)日：2013-07-23

申请号：US12192702

申请日：2008-08-15

Applicant: Pao-Huei Chang Chien ,  Ping-Cheng Hu ,  Chien-Wen Chen ,  Hsu-Yang Lee

Inventor： Pao-Huei Chang Chien ,  Ping-Cheng Hu ,  Chien-Wen Chen ,  Hsu-Yang Lee

IPC: H01L23/495

CPC classification number: H01L21/4832 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/07802 ,  H01L2924/12041 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, a plurality of leads, a chip, and a package body. The die pad includes: (1) a peripheral edge region defining, a cavity with a cavity bottom including a central portion; (2) an upper sloped portion; and (3) a lower sloped portion. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the central portion of the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body.

Abstract translation: 描述半导体封装和相关方法。 在一个实施例中，封装包括管芯焊盘，多个引线，芯片和封装体。 所述管芯焊盘包括：（1）外围边缘区域，其限定具有包括中心部分的空腔底部的空腔; （2）上倾斜部分; 和（3）下倾斜部分。 每个引线包括上倾斜部分和下倾斜部分。 芯片设置在空腔底部的中心部分并且连接到引线。 封装体形成在芯片和引线上，基本上填充空腔，并且基本上覆盖芯片焊盘和引线的上倾斜部分。 芯片焊盘和引线的下倾斜部分至少部分地从封装主体的下表面向外延伸。

公开(公告)号：US08115285B2

公开(公告)日：2012-02-14

申请号：US12192805

申请日：2008-08-15

Applicant: Chien-Wen Chen ,  Yi-Shao Lai ,  Hsiao-Chuan Chang ,  Tsung-Yueh Tsai ,  Pao-Huei Chang Chien ,  Ping-Cheng Hu ,  Hsu-Yang Lee

Inventor： Chien-Wen Chen ,  Yi-Shao Lai ,  Hsiao-Chuan Chang ,  Tsung-Yueh Tsai ,  Pao-Huei Chang Chien ,  Ping-Cheng Hu ,  Hsu-Yang Lee

IPC: H01L21/00

CPC classification number: H01L21/4832 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/07802 ,  H01L2924/12041 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, multiple leads, a chip, a package body, and a protective layer. The die pad includes an upper sloped portion, a lower sloped portion, and a peripheral edge region defining a cavity with a cavity bottom. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body. The protective layer substantially covers the lower sloped portion and the lower surface of at least one lead.

Abstract translation: 描述半导体封装和相关方法。 在一个实施例中，封装包括管芯焊盘，多个引线，芯片，封装体和保护层。 管芯焊盘包括上倾斜部分，下倾斜部分和限定具有空腔底部的空腔的周边边缘区域。 每个引线包括上倾斜部分和下倾斜部分。 芯片设置在腔体底部并耦合到引线。 封装体形成在芯片和引线上，基本上填充空腔，并且基本上覆盖芯片焊盘和引线的上倾斜部分。 芯片焊盘和引线的下倾斜部分至少部分地从封装主体的下表面向外延伸。 保护层基本上覆盖至少一个引线的下倾斜部分和下表面。

公开(公告)号：US20100044843A1

公开(公告)日：2010-02-25

申请号：US12425635

申请日：2009-04-17

Applicant: Pao-Huei Chang Chien ,  Ping-Cheng Hu ,  Po-Shing Chiang ,  Wei-Lun Cheng

Inventor： Pao-Huei Chang Chien ,  Ping-Cheng Hu ,  Po-Shing Chiang ,  Wei-Lun Cheng

IPC: H01L23/495 ,  H01L21/60 ,  H01L21/56

CPC classification number: H01L21/4832 ,  H01L23/49503 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45164 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

Abstract: The advanced quad flat non-leaded package structure includes a carrier, a chip, a plurality of wires, and a molding compound. The carrier includes a die pad and a plurality of leads. The leads include first leads disposed around the die pad, second leads disposed around the first leads and at least an embedded lead portion between the first leads and the second leads. The wires are disposed between the chip, the first leads and the embedded lead portion. The advanced quad flat non-leaded package structures designed with the embedded lead portion can provide better electrical connection.

Abstract translation: 先进的四边形扁平无铅封装结构包括载体，芯片，多根导线和模塑料。 载体包括管芯焊盘和多个引线。 引线包括围绕芯片焊盘设置的第一引线，围绕第一引线设置的第二引线和至少在第一引线和第二引线之间的嵌入引线部分。 电线布置在芯片，第一引线和嵌入引线部分之间。 采用嵌入式引线部分设计的先进的四边形扁平非引线封装结构可以提供更好的电气连接。

公开(公告)号：US20130009313A1

公开(公告)日：2013-01-10

申请号：US13433061

申请日：2012-03-28

Applicant: Po-Shing Chiang ,  Ping-Cheng Hu ,  Yu-Fang Tsai

Inventor： Po-Shing Chiang ,  Ping-Cheng Hu ,  Yu-Fang Tsai

IPC: H01L23/48 ,  H01L21/60

CPC classification number: H01L23/488 ,  H01L21/4832 ,  H01L21/56 ,  H01L23/49541 ,  H01L23/49582 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A semiconductor device package including a substrate, first and second solder joints, a die pad, leads and enhancement elements surrounding the die pad, a chip electrically connected to the leads, and a package body encapsulating the chip, portions of the leads, and portions of the enhancement elements, but leaving exposed at least a side surface of each enhancement element. Side surfaces of the enhancement elements and the package body are coplanar. The substrate includes first pads corresponding to the leads and second pads corresponding to the enhancement elements. The first solder joints are disposed between the first pads and the leads. The second solder joints are disposed between the second pads and the enhancement elements. The second solder joints contact side surfaces of the enhancement elements. The surface area of the second pads is greater than the surface area of the corresponding enhancement elements.

Abstract translation: 一种半导体器件封装，包括基板，第一和第二焊点，芯片焊盘，引线和围绕芯片焊盘的增强元件，与引线电连接的芯片以及封装芯片，引线部分和部分 的增强元件，但是留下每个增强元件的至少一个侧表面。 增强元件和封装主体的侧表面是共面的。 衬底包括对应于引线的第一焊盘和对应于增强元件的第二焊盘。 第一焊点设置在第一焊盘和引线之间。 第二焊点设置在第二焊盘和增强元件之间。 第二焊点接触增强元件的侧表面。 第二焊盘的表面积大于相应增强元件的表面积。

公开(公告)号：US20120119342A1

公开(公告)日：2012-05-17

申请号：US12944695

申请日：2010-11-11

Applicant: Pao-Huei Chang Chien ,  Ping-Cheng Hu ,  Po-Shing Chiang ,  Wei-Lun Cheng ,  Hsueh-Te Wang ,  Hsiao-Chuan Chang ,  Tsung-Yueh Tsai ,  Yi-Shao Lai ,  Ping-Feng Yang

Inventor： Pao-Huei Chang Chien ,  Ping-Cheng Hu ,  Po-Shing Chiang ,  Wei-Lun Cheng ,  Hsueh-Te Wang ,  Hsiao-Chuan Chang ,  Tsung-Yueh Tsai ,  Yi-Shao Lai ,  Ping-Feng Yang

IPC: H01L23/495 ,  H01L21/58 ,  H01L21/56

CPC classification number: H01L21/4832 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: The advanced quad flat non-leaded package structure includes a carrier, a chip, a plurality of wires, and a molding compound. The carrier includes a die pad and a plurality of leads. The inner leads of the leads are designed to possess incurved sidewalls for enhancing the adhesion between the inner leads and the surrounding molding compound.

Abstract translation: 先进的四边形扁平无铅封装结构包括载体，芯片，多根导线和模塑料。 载体包括管芯焊盘和多个引线。 引线的内引线被设计成具有弯曲的侧壁，用于增强内引线和周围模塑料之间的粘附。

公开(公告)号：US08120152B2

公开(公告)日：2012-02-21

申请号：US12192761

申请日：2008-08-15

Applicant: Pao-Huei Chang Chien ,  Ping-Cheng Hu ,  Chien-Wen Chen

Inventor： Pao-Huei Chang Chien ,  Ping-Cheng Hu ,  Chien-Wen Chen

IPC: H01L23/495

CPC classification number: H01L21/4832 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/07802 ,  H01L2924/12041 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, a first plurality of leads disposed in a lead placement area around the die pad, a second plurality of leads disposed in corner regions of the lead placement area, a semiconductor chip on the die pad and coupled to each lead, and a package body. Each lead includes an upper sloped portion and a lower sloped portion. An average of surface areas of lower surfaces of each of the second plurality of leads is at least twice as large as an average of surface areas of lower surfaces of each of the first plurality of leads. The package body substantially covers the upper sloped portions of the leads. The lower sloped portions of the leads at least partially extend outwardly from a lower surface of the package body.

Abstract translation: 描述半导体封装和相关方法。 在一个实施例中，封装包括管芯焊盘，设置在管芯焊盘周围的引线放置区域中的第一多个引线，设置在引线放置区域的拐角区域中的第二多个引线，管芯焊盘上的半导体芯片， 连接到每个引线和一个封装体。 每个引线包括上倾斜部分和下倾斜部分。 第二多个引线中的每一个的下表面的平均面积至少是第一多个引线中的每一个的下表面的平均表面积的两倍。 封装主体基本上覆盖引线的上倾斜部分。 引线的下倾斜部分至少部分地从包装体的下表面向外延伸。

公开(公告)号：US20100258921A1

公开(公告)日：2010-10-14

申请号：US12550655

申请日：2009-08-31

Applicant: PAO-HUEI CHANG CHIEN ,  PING-CHENG HU ,  PO-SHING CHIANG ,  WEI-LUN CHENG

Inventor： PAO-HUEI CHANG CHIEN ,  PING-CHENG HU ,  PO-SHING CHIANG ,  WEI-LUN CHENG

IPC: H01L23/495 ,  H01L21/60

CPC classification number: H01L21/4832 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49582 ,  H01L24/28 ,  H01L24/48 ,  H01L24/92 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48257 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: The advanced quad flat non-leaded package structure includes a carrier, a chip, a plurality of wires, and a molding compound. The carrier includes a die pad and a plurality of leads. The inner leads of the leads electively have a plurality of locking grooves for enhancing the adhesion between the inner leads and the surrounding molding compound.

Abstract translation: 先进的四边形扁平无铅封装结构包括载体，芯片，多根导线和模塑料。 载体包括管芯焊盘和多个引线。 引线的内引线选择性地具有多个锁定槽，用于增强内引线和周围模塑料之间的粘附。

公开(公告)号：US20130241041A1

公开(公告)日：2013-09-19

申请号：US13421570

申请日：2012-03-15

Applicant: Lin-Wang Yu ,  Ping-Cheng Hu ,  Che-Chin Chang ,  Yu-Fang Tsai

Inventor： Lin-Wang Yu ,  Ping-Cheng Hu ,  Che-Chin Chang ,  Yu-Fang Tsai

IPC: H01L23/495 ,  H01L21/60

CPC classification number: H01L24/97 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49579 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/78 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/78251 ,  H01L2224/83447 ,  H01L2224/8346 ,  H01L2224/8385 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2224/85805 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/45099

Abstract: A semiconductor package with a die pad, a die disposed on the die pad, and a first lead disposed about the die pad. The first lead includes a contact element, an extension element extending substantially in the direction of the die pad, and a concave surface disposed between the contact element and the extension element. A second lead having a concave surface is also disposed about the die pad. The first lead concave surface is opposite in direction to the second lead concave surface.

Abstract translation: 具有管芯焊盘的半导体封装，设置在管芯焊盘上的管芯和围绕管芯焊盘设置的第一引线。 第一引线包括接触元件，基本上沿芯片焊盘的方向延伸的延伸元件，以及设置在接触元件和延伸元件之间的凹表面。 具有凹面的第二引线也围绕芯片焊盘设置。 第一引线凹面与第二引线凹面的方向相反。

公开(公告)号：US08502363B2

公开(公告)日：2013-08-06

申请号：US13433061

申请日：2012-03-28

Applicant: Po-Shing Chiang ,  Ping-Cheng Hu ,  Yu-Fang Tsai

Inventor： Po-Shing Chiang ,  Ping-Cheng Hu ,  Yu-Fang Tsai

IPC: H01L23/495 ,  H01L21/00 ,  H01R9/00

CPC classification number: H01L23/488 ,  H01L21/4832 ,  H01L21/56 ,  H01L23/49541 ,  H01L23/49582 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A semiconductor device package including a substrate, first and second solder joints, a die pad, leads and enhancement elements surrounding the die pad, a chip electrically connected to the leads, and a package body encapsulating the chip, portions of the leads, and portions of the enhancement elements, but leaving exposed at least a side surface of each enhancement element. Side surfaces of the enhancement elements and the package body are coplanar. The substrate includes first pads corresponding to the leads and second pads corresponding to the enhancement elements. The first solder joints are disposed between the first pads and the leads. The second solder joints are disposed between the second pads and the enhancement elements. The second solder joints contact side surfaces of the enhancement elements. The surface area of the second pads is greater than the surface area of the corresponding enhancement elements.

Abstract translation: 一种半导体器件封装，包括基板，第一和第二焊点，芯片焊盘，引线和围绕芯片焊盘的增强元件，与引线电连接的芯片以及封装芯片，引线部分和部分 的增强元件，但是留下每个增强元件的至少一个侧表面。 增强元件和封装主体的侧表面是共面的。 衬底包括对应于引线的第一焊盘和对应于增强元件的第二焊盘。 第一焊点设置在第一焊盘和引线之间。 第二焊点设置在第二焊盘和增强元件之间。 第二焊点接触增强元件的侧表面。 第二焊盘的表面积大于相应增强元件的表面积。

公开(公告)号：US08106492B2

公开(公告)日：2012-01-31

申请号：US12550645

申请日：2009-08-31

Applicant: Pao-Huei Chang Chien ,  Ping-Cheng Hu ,  Po-Shing Chiang ,  Wei-Lun Cheng

Inventor： Pao-Huei Chang Chien ,  Ping-Cheng Hu ,  Po-Shing Chiang ,  Wei-Lun Cheng

IPC: H01L23/495 ,  H01L23/48

CPC classification number: H01L21/4832 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49582 ,  H01L24/28 ,  H01L24/48 ,  H01L24/92 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48257 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: The advanced quad flat non-leaded package structure includes a carrier having a die pad and a plurality of leads, at least a chip, a plurality of wires, and a molding compound. The rough surface of the carrier enhances the adhesion between the carrier and the surrounding molding compound.

Abstract translation: 先进的四边形扁平非铅封装结构包括具有管芯焊盘和多个引线，至少芯片，多根电线和模塑料的载体。 载体的粗糙表面增强了载体和周围模塑料之间的粘合性。