公开(公告)号：US07955968B2

公开(公告)日：2011-06-07

申请号：US12399372

申请日：2009-03-06

申请人： Pak K. Leung ,  Terry G. Sparks ,  David V. Horak ,  Stephen M. Gates

发明人： Pak K. Leung ,  Terry G. Sparks ,  David V. Horak ,  Stephen M. Gates

IPC分类号： H01L21/4763

CPC分类号： H01L21/76828 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76835 ,  H01L2221/1036 ,  Y10T29/49224

摘要： A method and apparatus are described for fabricating an ultra low-k interconnect structure by depositing and curing a first via layer (43) of ultra low dielectric constant (ULK) material, depositing a second uncured trench layer (51) of the same ULK material, selectively etching a via opening (62) and trench opening (72) with a dual damascene etch process which uses a trench etch end point signal from the chemical differences between uncured trench layer (51) and the underlying cured via layer (43), and then curing the second trench layer (83) before forming an interconnect structure (91) by filling the trench opening (72) and via opening (62) with an interconnection material so that there is no additional interface or higher dielectric constant material left behind.

摘要翻译： 描述了通过沉积和固化超低介电常数（ULK）材料的第一通孔层（43）来制造超低k互连结构的方法和装置，沉积相同ULK材料的第二未固化沟槽层（51） 通过使用来自未固化沟槽层（51）和下面的固化通孔层（43）之间的化学差异的沟槽蚀刻终点信号的双镶嵌蚀刻工艺来选择性地蚀刻通孔开口（62）和沟槽开口（72） 然后在通过用互连材料填充沟槽开口（72）和通孔开口（62）形成互连结构（91）之前固化第二沟槽层（83），使得不存在附加的界面或更高的介电常数材料留下 。

公开(公告)号：US20100227471A1

公开(公告)日：2010-09-09

申请号：US12399372

申请日：2009-03-06

申请人： Pak K. Leung ,  Terry G. Sparks ,  David V. Horak ,  Steven M. Gates

发明人： Pak K. Leung ,  Terry G. Sparks ,  David V. Horak ,  Steven M. Gates

IPC分类号： H01L21/4763 ,  H01R43/00

CPC分类号： H01L21/76828 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76835 ,  H01L2221/1036 ,  Y10T29/49224

摘要： A method and apparatus are described for fabricating an ultra low-k interconnect structure by depositing and curing a first via layer (43) of ultra low dielectric constant (ULK) material, depositing a second uncured trench layer (51) of the same ULK material, selectively etching a via opening (62) and trench opening (72) with a dual damascene etch process which uses a trench etch end point signal from the chemical differences between uncured trench layer (51) and the underlying cured via layer (43), and then curing the second trench layer (83) before forming an interconnect structure (91) by filling the trench opening (72) and via opening (62) with an interconnection material so that there is no additional interface or higher dielectric constant material left behind.

摘要翻译： 描述了通过沉积和固化超低介电常数（ULK）材料的第一通孔层（43）来制造超低k互连结构的方法和装置，沉积相同ULK材料的第二未固化沟槽层（51） 通过使用来自未固化沟槽层（51）和下面的固化通孔层（43）之间的化学差异的沟槽蚀刻终点信号的双镶嵌蚀刻工艺来选择性地蚀刻通孔开口（62）和沟槽开口（72） 然后在通过用互连材料填充沟槽开口（72）和通孔开口（62）形成互连结构（91）之前固化第二沟槽层（83），使得不存在附加的界面或更高的介电常数材料留下 。

公开(公告)号：US20090325106A1

公开(公告)日：2009-12-31

申请号：US12147889

申请日：2008-06-27

申请人： Willard E. Conley ,  Terry G. Sparks ,  William J. Taylor, JR.

发明人： Willard E. Conley ,  Terry G. Sparks ,  William J. Taylor, JR.

IPC分类号： H01L21/02

CPC分类号： H01L21/0332 ,  H01L21/2652 ,  H01L29/78

摘要： A semiconductor fabrication method that includes forming a patterned mask (62, 72) by spin coating a developable hard mask layer (32) and a resist layer (42) over a semiconductor substrate (4). Subsequently, the resist layer (42) is exposed and developed to form a patterned resist layer (62), where the development step also removes the underlying hard mask layer (32), thereby forming a patterned mask (62, 72) which defines a void or printed feature to expose a region (97) over the semiconductor substrate which may be implanted, etched or otherwise processed.

摘要翻译： 一种半导体制造方法，包括通过在半导体衬底（4）上旋涂可显影硬掩模层（32）和抗蚀剂层（42）来形成图案化掩模（62,72）。 随后，曝光和显影抗蚀剂层（42）以形成图案化的抗蚀剂层（62），其中显影步骤还去除下面的硬掩模层（32），由此形成图案化掩模（62,72），其限定了 空隙或印刷特征以暴露可以被植入，蚀刻或以其他方式处理的半导体衬底上的区域（97）。

公开(公告)号：US06245686B1

公开(公告)日：2001-06-12

申请号：US09586828

申请日：2000-06-05

申请人： Jeffrey D. Rose ,  Michael J. Hartig ,  David G. Farber ,  Danny R. Babbitt ,  Jason A. Rivers ,  Ai Koh ,  Terry G. Sparks

发明人： Jeffrey D. Rose ,  Michael J. Hartig ,  David G. Farber ,  Danny R. Babbitt ,  Jason A. Rivers ,  Ai Koh ,  Terry G. Sparks

IPC分类号： H01L21302

CPC分类号： H01J37/321 ,  H01L21/31116

摘要： A process for forming a semiconductor device includes placing a substrate (104) into an apparatus (300), creating a plasma, and processing the substrate (104). The apparatus (300) includes an electromagnetic source (120), a bulk material (302), and a first barrier layer (304). The bulk material (302) is between the electromagnetic source (120) and an interior (126) of the apparatus (300). The first barrier layer (304) is between the bulk material (302) and the interior (126). A process for operating an apparatus (300) includes forming a polymer layer along an inorganic layer (302, 306or 702), wherein the polymer layer is formed within the apparatus (300); removing the polymer layer to expose the inorganic layer (302, 306, or 702); and etching at least a portion of the exposed inorganic layer (302, 306, or 702). Typically, the inorganic layer (203, 306, or 702) is semiconductive or resistive.

摘要翻译： 一种用于形成半导体器件的工艺包括将衬底（104）放入设备（300）中，产生等离子体，以及处理衬底（104）。 装置（300）包括电磁源（120），散装材料（302）和第一阻挡层（304）。 散装材料（302）位于电磁源（120）和装置（300）的内部（126）之间。 第一阻挡层（304）在散装材料（302）和内部（126）之间。 用于操作设备（300）的方法包括沿着无机层（302,306或702）形成聚合物层，其中聚合物层形成在设备（300）内; 除去聚合物层以暴露无机层（302,306或702）; 并蚀刻所述暴露的无机层（302,306或702）的至少一部分。 通常，无机层（203,306或702）是半导体或电阻的。

公开(公告)号：US20080113505A1

公开(公告)日：2008-05-15

申请号：US11558988

申请日：2006-11-13

申请人： Terry G. Sparks ,  Syed M. Alam ,  Ritwik Chatterjee ,  Shahid Rauf

发明人： Terry G. Sparks ,  Syed M. Alam ,  Ritwik Chatterjee ,  Shahid Rauf

IPC分类号： H01L21/768

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for achieving a through-substrate via through a substrate having active circuitry on a first major surface begins by forming a hole into the substrate through the first major surface. The hole is lined with a conductive layer. A dielectric layer is deposited over the conductive layer. This deposition is performed in a manner that causes the dielectric layer to be substantially conformal. Conductive material is formed over first dielectric layer. A second major surface of the substrate is etched to expose the conductive material.

摘要翻译： 通过在第一主表面上具有有源电路的基板实现贯通基板通孔的方法首先通过第一主表面在基板中形成孔。 孔内衬有导电层。 介电层沉积在导电层上。 这种沉积以使介电层基本上保形的方式进行。 导电材料形成在第一介电层上。 蚀刻衬底的第二主表面以暴露导电材料。

公开(公告)号：US06858542B2

公开(公告)日：2005-02-22

申请号：US10346263

申请日：2003-01-17

申请人： Terry G. Sparks ,  Ajay Singhal ,  Kirk J. Strozewski

发明人： Terry G. Sparks ,  Ajay Singhal ,  Kirk J. Strozewski

IPC分类号： G01N20060101 ,  G03F7/00 ,  G03F7/36 ,  H01L21/027 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311

CPC分类号： H01L21/3085 ,  H01L21/3083 ,  H01L21/31144 ,  Y10S438/947 ,  Y10S438/976 ,  Y10S438/978

摘要： A semiconductor fabrication method that includes forming a film (109) comprising an imaging layer (112) and an under layer (110) over a semiconductor substrate (102). The imaging layer (112) is patterned to produce a printed feature (116) having a printed dimension (124). The under layer (110) is then processed to produce a sloped sidewall void (120) in the under layer (110) wherein the void (120) has a finished dimension (126) in proximity to the underlying substrate that is less than the printed dimension. Processing the under layer (110) may include exposing the wafer to high density low pressure N2 plasma.

摘要翻译： 一种半导体制造方法，包括在半导体衬底（102）上形成包括成像层（112）和下层（110）的膜（109）。 成像层（112）被图案化以产生具有印刷尺寸（124）的印刷特征（116）。 然后，下层（110）被处理以在下层（110）中产生倾斜的侧壁空隙（120），其中空隙（120）具有接近底层基底的成品尺寸（126），小于印刷 尺寸。 处理底层（110）可以包括将晶片暴露于高密度低压N2等离子体。

公开(公告)号：US20110027999A1

公开(公告)日：2011-02-03

申请号：US12377348

申请日：2006-08-16

申请人： Terry G. Sparks ,  Rauf Shahid

发明人： Terry G. Sparks ,  Rauf Shahid

IPC分类号： H01L21/465

CPC分类号： H01L21/3065 ,  C23F4/00 ,  H01L21/31116 ,  H01L21/32136

摘要： The present invention provides a method for etching a substrate in the manufacture of a semiconductor device, the method comprising contacting a surface of the substrate with ions extracted from a plasma formed from a gas comprising one or more of an oxygen-containing species, a nitrogen-containing species and an inert gas, and separately contacting the surface of the substrate with a plasma formed from a gas comprising a fluorine-containing species.

摘要翻译： 本发明提供一种在半导体器件的制造中蚀刻衬底的方法，所述方法包括使衬底的表面与从包含一种或多种含氧物质，氮气的气体形成的等离子体提取的离子接触 和惰性气体，并且分别使基板的表面与由包含含氟物质的气体形成的等离子体接触。

公开(公告)号：US07544605B2

公开(公告)日：2009-06-09

申请号：US11562161

申请日：2006-11-21

申请人： Terry G. Sparks ,  Shahid Rauf

发明人： Terry G. Sparks ,  Shahid Rauf

IPC分类号： H01L21/20

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552

摘要： A method of forming a semiconductor device includes forming active circuitry over a semiconductor substrate, wherein the semiconductor substrate has a first major surface and a second major surface and the first active circuitry is formed over the first major surface of the semiconductor substrate. A via is formed within the first semiconductor substrate, wherein the via extends from the first active circuitry to the second major surface of the first semiconductor substrate. A dielectric layer is formed over the second major surface and adjacent the first via. The dielectric layer may include nitrogen and silicon and may be formed by a low pressure, low temperature, or both plasma process.

摘要翻译： 形成半导体器件的方法包括在半导体衬底上形成有源电路，其中半导体衬底具有第一主表面和第二主表面，并且第一有源电路形成在半导体衬底的第一主表面上。 通孔形成在第一半导体衬底内，其中通孔从第一有源电路延伸到第一半导体衬底的第二主表面。 介电层形成在第二主表面上并与第一通孔相邻。 电介质层可以包括氮和硅，并且可以通过低压，低温或两种等离子体工艺形成。

公开(公告)号：US06838354B2

公开(公告)日：2005-01-04

申请号：US10327403

申请日：2002-12-20

申请人： Cindy K. Goldberg ,  Stanley Michael Filipiak ,  John C. Flake ,  Yeong-Jyh T. Lii ,  Bradley P. Smith ,  Yuri E. Solomentsev ,  Terry G. Sparks ,  Kirk J. Strozewski ,  Kathleen C. Yu

发明人： Cindy K. Goldberg ,  Stanley Michael Filipiak ,  John C. Flake ,  Yeong-Jyh T. Lii ,  Bradley P. Smith ,  Yuri E. Solomentsev ,  Terry G. Sparks ,  Kirk J. Strozewski ,  Kathleen C. Yu

IPC分类号： H01L21/288 ,  H01L21/768 ,  H01L21/76

CPC分类号： H01L21/76844 ,  H01L21/288 ,  H01L21/7682 ,  H01L21/76849 ,  H01L21/76874

摘要： Dummy features (64, 65, 48a, 48b) are formed within an interlevel dielectric layer (36). Passivation layers (32 and 54) are formed by electroless deposition to protect the underlying conductive regions (44, 48a, 48b and 30) from being penetrated from the air gaps (74). In addition, the passivation layers (32 and 54) overhang the underlying conductive regions (44, 48a, 48b and 30), thereby defining dummy features (65a, 65b and 67) adjacent the conductive regions (48a, 44 and 48b). The passivation layers (32 and 54) can be formed without additional patterning steps and help minimize misaligned vias from puncturing air gaps.

公开(公告)号：US20080119046A1

公开(公告)日：2008-05-22

申请号：US11562161

申请日：2006-11-21

申请人： Terry G. Sparks ,  Shahid Rauf

发明人： Terry G. Sparks ,  Shahid Rauf

IPC分类号： H01L21/768

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552

摘要： A method of forming a semiconductor device includes forming active circuitry over a semiconductor substrate, wherein the semiconductor substrate has a first major surface and a second major surface and the first active circuitry is formed over the first major surface of the semiconductor substrate. A via is formed within the first semiconductor substrate, wherein the via extends from the first active circuitry to the second major surface of the first semiconductor substrate. A dielectric layer is formed over the second major surface and adjacent the first via. The dielectric layer may include nitrogen and silicon and may be formed by a low pressure, low temperature, or both plasma process.

摘要翻译： 形成半导体器件的方法包括在半导体衬底上形成有源电路，其中半导体衬底具有第一主表面和第二主表面，并且第一有源电路形成在半导体衬底的第一主表面上。 通孔形成在第一半导体衬底内，其中通孔从第一有源电路延伸到第一半导体衬底的第二主表面。 介电层形成在第二主表面上并与第一通孔相邻。 电介质层可以包括氮和硅，并且可以通过低压，低温或两种等离子体工艺形成。