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    IN-SITU BARRIER OXIDATION TECHNIQUES AND CONFIGURATIONS
    1.
    发明申请
    IN-SITU BARRIER OXIDATION TECHNIQUES AND CONFIGURATIONS 审中-公开
    现场障碍物氧化技术和配置

    公开(公告)号：US20130320349A1

    公开(公告)日：2013-12-05

    申请号：US13484215

    申请日：2012-05-30

    申请人： Paul Saunier ,  Andrew A. Ketterson

    发明人： Paul Saunier ,  Andrew A. Ketterson

    IPC分类号： H01L21/335 ,  H01L21/336 ,  H01L29/778

    CPC分类号： H01L29/7787 ,  H01L21/02241 ,  H01L29/2003 ,  H01L29/66462

    摘要： Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device. The IC device may include a buffer layer disposed on a substrate, the buffer layer including gallium (Ga) and nitrogen (N), a barrier layer disposed on the buffer layer, the barrier layer including aluminum (Al) and nitrogen (N), wherein the barrier layer includes an oxidized portion of the barrier layer, a gate dielectric disposed on the oxidized portion of the barrier layer, and a gate electrode disposed on the gate dielectric, wherein the oxidized portion of the barrier layer is disposed in a gate region between the gate electrode and the buffer layer.

    摘要翻译： 本公开的实施例描述了集成电路（IC）装置的装置，方法和系统。 IC器件可以包括设置在衬底上的缓冲层，缓冲层包括镓（Ga）和氮（N），阻挡层设置在缓冲层上，阻挡层包括铝（Al）和氮（N） 其中所述阻挡层包括所述阻挡层的氧化部分，设置在所述阻挡层的氧化部分上的栅极电介质和设置在所述栅极电介质上的栅电极，其中所述阻挡层的氧化部分设置在栅极区域 在栅电极和缓冲层之间。

    Device structure including high-thermal-conductivity substrate
    2.
    发明授权
    Device structure including high-thermal-conductivity substrate 有权
    器件结构包括高导热基板

    公开(公告)号：US08350295B1

    公开(公告)日：2013-01-08

    申请号：US12030594

    申请日：2008-02-13

    申请人： Paul Saunier ,  Edward Beam ,  Deep Dumka

    发明人： Paul Saunier ,  Edward Beam ,  Deep Dumka

    IPC分类号： H01L29/66

    CPC分类号： H01L29/66318 ,  H01L29/7371

    摘要： Methods and apparatuses for forming a device structure including a high-thermal-conductivity substrate are disclosed herein. A method forming such a device structure may comprise forming an active layer over a first substrate in a manner such that a frontside of the active layer faces the first substrate and a backside of the active layer faces away from the first substrate, forming a second substrate over the backside of the active layer, and removing the first substrate to expose the frontside of the active layer. Other embodiments are described and claimed.

    摘要翻译： 本文公开了用于形成包括高导热性基板的器件结构的方法和装置。 形成这种器件结构的方法可以包括以如下方式在第一衬底上形成有源层，使得有源层的前侧面向第一衬底，并且有源层的背面背离第一衬底，形成第二衬底 在有源层的背面上，并且移除第一衬底以暴露有源层的前侧。 描述和要求保护其他实施例。

    Method of fabricating an integrated circuit for providing low-noise and high-power microwave operation
    4.
    发明授权
    Method of fabricating an integrated circuit for providing low-noise and high-power microwave operation 失效
    制造用于提供低噪声和大功率微波操作的集成电路的方法

    公开(公告)号：US5254492A

    公开(公告)日：1993-10-19

    申请号：US973906

    申请日：1992-11-10

    申请人： Hua Q. Tserng ,  Paul Saunier

    发明人： Hua Q. Tserng ,  Paul Saunier

    IPC分类号： H01L21/8252 ,  H01L21/8254 ,  H01L27/06 ,  H01L27/095 ,  H01L21/70

    CPC分类号： H01L27/0605 ,  H01L21/8252 ,  H01L21/8254 ,  H01L27/095 ,  Y10S148/072

    摘要： Generally, and in one form of the invention, an integrated circuit is disclosed for providing low-noise and high-power microwave operation comprising: an epitaxial material structure comprising a substrate 10, a low-noise channel layer 14, a low-noise buffer layer 16, a power channel layer 18, and a moderately doped wide bandgap layer 20; a first active region 24 comprising a first source contact 32 above the wide bandgap layer 22, a first drain contact 36 above the wide bandgap layer 22, wherein the first source contact 32 and the first drain contact 36 are alloyed and thereby driven into the material structure to make contact with the low-noise channel layer 14, and a first gate contact 28 to the low-noise buffer layer 16; and a second active region 26 comprising a second source contact 34 above the wide bandgap layer 22, a second drain contact 38 above the wide bandgap layer 22, wherein the second source contact 34 and the second drain contact 38 are alloyed and thereby driven into the material structure to make contact with the power channel layer 18, and a second gate contact 30 to the wide bandgap layer 22; wherein the first active region 24 and the second active region 26 are electrically isolated from one another, and whereby the integrated circuit is formed with all epitaxial layers formed during a single epitaxial growth cycle and is capable of providing low-noise, high-power, and switching operation at microwave frequencies.

    摘要翻译： 通常，在本发明的一种形式中，公开了一种用于提供低噪声和高功率微波操作的集成电路，其包括：外延材料结构，其包括衬底10，低噪声沟道层14，低噪声缓冲器 层16，功率沟道层18和适度掺杂的宽带隙层20; 第一有源区24包括宽带隙层22上方的第一源极接触32，宽带隙层22上方的第一漏极接触36，其中第一源极接触32和第一漏极接触36被合金化，从而被驱入材料 与低噪声信道层14接触的结构，以及到低噪声缓冲层16的第一栅极接触28; 以及第二有源区26，其包括宽带隙层22上方的第二源极接触34，在宽带隙层22上方的第二漏极接触38，其中第二源极接触34和第二漏极接触38被合金化，从而被驱动到 材料结构与功率沟道层18接触，第二栅极接触30与宽带隙层22接触; 其中第一有源区24和第二有源区26彼此电绝缘，由此集成电路形成有在单个外延生长周期期间形成的所有外延层，并且能够提供低噪声，大功率， 并在微波频率切换操作。

    Integrated circuit capable of low-noise and high-power microwave operation
    7.
    发明授权
    Integrated circuit capable of low-noise and high-power microwave operation 失效
    具有低噪声，高功率微波操作的集成电路

    公开(公告)号：US06215136B1

    公开(公告)日：2001-04-10

    申请号：US08089359

    申请日：1993-07-09

    申请人： Hua Quen Tserng ,  Paul Saunier

    发明人： Hua Quen Tserng ,  Paul Saunier

    IPC分类号： H01L31072

    CPC分类号： H01L27/0605 ,  H01L21/8252 ,  H01L21/8254 ,  H01L27/095 ,  Y10S148/072

    摘要： Generally, and in one form of the invention, an integrated circuit is disclosed for providing low-noise and high-power microwave operation comprising: an epitaxial material structure comprising a substrate 10, a low-noise channel layer 14, a low-noise buffer layer 16, a power channel layer 18, and a moderately doped wide bandgap layer 20; a first active region 24 comprising a first source contact 32 above the wide bandgap layer 22, a first drain contact 36 above the wide bandgap layer 22, wherein the first source contact 32 and the first drain contact 36 are alloyed and thereby driven into the material structure to make contact with the low-noise channel layer 14, and a first gate contact 28 to the low-noise buffer layer 16; and a second active region 26 comprising a second source contact 34 above the wide bandgap layer 22, a second drain contact 38 above the wide bandgap layer 22, wherein the second source contact 34 and the second drain contact 38 are alloyed and thereby driven into the material structure to make contact with the power channel layer 18, and a second gate contact 30 to the wide bandgap layer 22; wherein the first active region 24 and the second active region 26 are electrically isolated from one another, and whereby the integrated circuit is formed with all epitaxial layers formed during a single epitaxial growth cycle and is capable of providing low-noise, high-power, and switching operation at microwave frequencies.

    摘要翻译： 通常，在本发明的一种形式中，公开了一种用于提供低噪声和高功率微波操作的集成电路，其包括：外延材料结构，其包括衬底10，低噪声沟道层14，低噪声缓冲器 层16，功率沟道层18和适度掺杂的宽带隙层20; 第一有源区24包括宽带隙层22上方的第一源极接触32，宽带隙层22上方的第一漏极接触36，其中第一源极接触32和第一漏极接触36被合金化，从而被驱入材料 与低噪声信道层14接触的结构，以及到低噪声缓冲层16的第一栅极接触28; 以及第二有源区26，其包括宽带隙层22上方的第二源极接触34，在宽带隙层22上方的第二漏极接触38，其中第二源极接触34和第二漏极接触38被合金化，从而被驱动到 材料结构与功率沟道层18接触，第二栅极接触30与宽带隙层22接触; 其中第一有源区24和第二有源区26彼此电绝缘，由此集成电路形成有在单个外延生长周期期间形成的所有外延层，并且能够提供低噪声，大功率， 并在微波频率切换操作。

    GaAs FET with resistive AlGaAs
    8.
    发明授权
    GaAs FET with resistive AlGaAs 失效
    具有电阻AlGaAs的GaAs FET

    公开(公告)号：US5300795A

    公开(公告)日：1994-04-05

    申请号：US854169

    申请日：1992-03-20

    申请人： Paul Saunier ,  Hua Q. Tserng

    发明人： Paul Saunier ,  Hua Q. Tserng

    IPC分类号： H01L21/338 ,  H01L29/10 ,  H01L29/778 ,  H01L29/812 ,  H01L29/80 ,  H01L21/265 ,  H01L21/44 ,  H01L29/161

    CPC分类号： H01L29/1029 ,  H01L29/8128

    摘要： This is a FET device and the device comprises: a buffer layer 30; a channel layer 32 of doped narrow bandgap material over the buffer layer; and a resistive layer 34 of low doped wide bandgap material over the channel layer, the doping of the channel layer and the resistive layer being such that no significant transfer of electrons occurs between the resistive layer and the channel layer. This is also a method of making a FET device.

    摘要翻译： 这是一种FET器件，该器件包括：缓冲层30; 在缓冲层上的掺杂窄带隙材料的沟道层32; 以及在沟道层上的低掺杂宽带隙材料的电阻层34，沟道层和电阻层的掺杂使得在电阻层和沟道层之间不发生电子的显着转移。 这也是制造FET器件的方法。

    Multiple high electron mobility transistor structures without inverted heterojunctions
    9.
    发明授权
    Multiple high electron mobility transistor structures without inverted heterojunctions 失效
    多反向异质结的高电子迁移率晶体管结构

    公开(公告)号：US4558337A

    公开(公告)日：1985-12-10

    申请号：US615978

    申请日：1984-05-30

    申请人： Paul Saunier ,  Hung-Dah Shih

    发明人： Paul Saunier ,  Hung-Dah Shih

    IPC分类号： H01L29/812 ,  H01L21/338 ,  H01L29/778 ,  H01L29/80 ,  H01L29/205

    CPC分类号： H01L29/7785

    摘要： A multiple high electron mobility transistor structure without inverted heterojunctions is disclosed. Multiple normal heterojunctions of doped aluminum gallium arsenide grown on gallium arsenide without alternating inverted heterojunctions of gallium arsenide grown on doped aluminum gallium arsenide is achieved by grading undoped aluminum gallium arsenide from the doped aluminum gallium arsenide to the gallium arsenide to avoid an inverted heterojunction.

    摘要翻译： 公开了一种没有反相异质结的多重高电子迁移率晶体管结构。 通过将未掺杂的砷化镓从掺杂的砷化镓中分配到砷化镓，可以实现在砷化镓上生长的砷化镓上掺杂的砷化铝镓的多个正态异质结，而不需要在掺杂的砷化镓上生长砷化镓的交替反向异质结，从而避免反向异质结。

    HIGH ELECTRON MOBILITY TRANSISTOR STRUCTURE AND METHOD
    10.
    发明申请
    HIGH ELECTRON MOBILITY TRANSISTOR STRUCTURE AND METHOD 审中-公开

    公开(公告)号：US20130105817A1

    公开(公告)日：2013-05-02

    申请号：US13282424

    申请日：2011-10-26

    申请人： Paul Saunier

    发明人： Paul Saunier

    IPC分类号： H01L29/778

    CPC分类号： H01L29/778 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/7787

    摘要： Embodiments of the present disclosure describe structural configurations of an integrated circuit (IC) device such as a high electron mobility transistor (HEMT) switch device and method of fabrication. The IC device includes a buffer layer formed on a substrate, a channel layer formed on the buffer layer to provide a pathway for current flow in a transistor device, a spacer layer formed on the channel layer, a barrier layer formed on the spacer layer, the barrier layer including aluminum (Al), nitrogen (N), and at least one of indium (In) or gallium (Ga), a gate dielectric directly coupled with the spacer layer or the channel layer, and a gate formed on the gate dielectric, the gate being directly coupled with the gate dielectric. Other embodiments may also be described and/or claimed.