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    Programable interrupt controller
    1.
    发明授权
    Programable interrupt controller 失效
    可编程中断控制器

    公开(公告)号：US5261107A

    公开(公告)日：1993-11-09

    申请号：US825336

    申请日：1992-01-23

    申请人： Peter J. Klim ,  Avery M. Lyford ,  Dennis L. Moeller

    发明人： Peter J. Klim ,  Avery M. Lyford ,  Dennis L. Moeller

    IPC分类号： G06F13/24 ,  G06F13/26 ,  G06F9/46

    CPC分类号： G06F13/26 ,  G06F13/24

    摘要： A programmable interrupt controller having a plurality of interrupt request inquest inputs and an interrupt request output for connection to a central processing unit (CPU) includes means for interrupting the CPU over the interrupt request output responsive to an interrupt request from any one of the interrupt request inputs and a priority resolver for assigning a priority position to each of the interrupt request inputs to create an interrupt priority hierarchy. The interrupt controller is programmable such that each interrupt request input may be independently established as responsive to either edge-triggered or level-triggered interrupt requests on a per interrupt basis. An initialization command word register of the interrupt controller has a bit corresponding to each of the interrupt request inputs. Programming each of the bits of the register to one of two states determines whether corresponding interrupt request inputs are edge-sensitive or level-sensitive.

    摘要翻译： 具有多个中断请求查询输入的可编程中断控制器和用于连接到中央处理单元（CPU）的中断请求输出包括响应于来自任一中断请求的中断请求而中断CPU的中断请求输出的装置 输入和优先级分解器，用于将优先级位置分配给每个中断请求输入以创建中断优先级层次。 中断控制器是可编程的，使得每个中断请求输入可以独立地建立为响应于每个中断的边沿触发或电平触发中断请求。 中断控制器的初始化命令字寄存器具有与每个中断请求输入相对应的位。 将寄存器的每个位编程为两种状态之一决定了相应的中断请求输入是边沿敏感还是对电平敏感。

    Structure for automated transistor tuning in an integrated circuit design
    3.
    发明授权
    Structure for automated transistor tuning in an integrated circuit design 有权
    用于集成电路设计中自动晶体管调谐的结构

    公开(公告)号：US08010932B2

    公开(公告)日：2011-08-30

    申请号：US12130476

    申请日：2008-05-30

    申请人： Christopher M. Durham ,  Peter J. Klim ,  Robert N. L. Krentler

    发明人： Christopher M. Durham ,  Peter J. Klim ,  Robert N. L. Krentler

    IPC分类号： G06F9/455

    CPC分类号： G06F17/5063

    摘要： A design structure for tuning an integrated circuit design holds a reference clock signal constant across the integrated circuit design and, while the reference clock signal is held constant, optimizes transistors forming a register within the integrated circuit design and thereafter optimizes transistors forming one or more clock buffers coupled to the reference clock signal.

    摘要翻译： 用于调谐集成电路设计的设计结构在集成电路设计中保持参考时钟信号恒定，并且当参考时钟信号保持恒定时，优化在集成电路设计中形成寄存器的晶体管，然后优化形成一个或多个时钟的晶体管 耦合到参考时钟信号的缓冲器。

    Structure for Reduced Area Active Above-Ground and Below-Supply Noise Suppression Circuits
    4.
    发明申请
    Structure for Reduced Area Active Above-Ground and Below-Supply Noise Suppression Circuits 失效
    减小区域有效地面和低于电源噪声抑制电路的结构

    公开(公告)号：US20090106708A1

    公开(公告)日：2009-04-23

    申请号：US12129532

    申请日：2008-05-29

    申请人： Rafik F. Dagher ,  Christopher M. Durham ,  Peter J. Klim

    发明人： Rafik F. Dagher ,  Christopher M. Durham ,  Peter J. Klim

    IPC分类号： G06F17/50 ,  H03K17/16

    CPC分类号： H03K19/00361

    摘要： A design structure for noise suppression. A design structure has a noise detection unit, a noise suppression unit, and a control unit. The noise suppression unit has an input and an output, wherein the input of the noise detection unit is connected to a signal and generates a signal change at the output if a change in the signal is detected. The noise suppression unit has an input and an output, wherein the input of the noise suppression unit is connected to the output of the noise detection unit and generates a correction to the signal in response to detecting the signal change at the output of the noise detection unit. The control unit has an input and an output, wherein input to the control unit is connected to the signal and turns off the noise suppression unit if a state change is detected in the signal.

    摘要翻译： 噪声抑制的设计结构。 设计结构具有噪声检测单元，噪声抑制单元和控制单元。 噪声抑制单元具有输入和输出，其中噪声检测单元的输入连接到信号，并且如果检测到信号的变化则在输出端产生信号变化。 噪声抑制单元具有输入和输出，其中噪声抑制单元的输入连接到噪声检测单元的输出，并且响应于检测到噪声检测的输出处的信号变化而产生对该信号的校正 单元。 控制单元具有输入和输出，其中控制单元的输入连接到信号，并且如果在信号中检测到状态改变则关闭噪声抑制单元。

    REDUCED AREA ACTIVE ABOVE-GROUND AND BELOW-SUPPLY NOISE SUPPRESSION CIRCUITS
    5.
    发明申请
    REDUCED AREA ACTIVE ABOVE-GROUND AND BELOW-SUPPLY NOISE SUPPRESSION CIRCUITS 失效
    减少区域上下地下和低电压噪声抑制电路

    公开(公告)号：US20090102509A1

    公开(公告)日：2009-04-23

    申请号：US11877219

    申请日：2007-10-23

    申请人： Rafik Dagher ,  Christopher M. Durham ,  Peter J. Klim

    发明人： Rafik Dagher ,  Christopher M. Durham ,  Peter J. Klim

    IPC分类号： H03K17/16 ,  H03K19/003

    CPC分类号： H03K19/00361

    摘要： A method and apparatus for noise suppression. A circuit has a noise detection unit, a noise suppression unit, and a control unit. The noise suppression unit has an input and an output, wherein the input of the noise detection unit is connected to a signal and generates a signal change at the output if a change in the signal is detected. The noise suppression unit has an input and an output, wherein the input of the noise suppression unit is connected to the output of the noise detection unit and generates a correction to the signal in response to detecting the signal change at the output of the noise detection unit. The control unit has an input and an output, wherein input to the control unit is connected to the signal and turns off the noise suppression unit if a state change is detected in the signal.

    摘要翻译： 一种用于噪声抑制的方法和装置。 电路具有噪声检测单元，噪声抑制单元和控制单元。 噪声抑制单元具有输入和输出，其中噪声检测单元的输入连接到信号，并且如果检测到信号的变化则在输出端产生信号变化。 噪声抑制单元具有输入和输出，其中噪声抑制单元的输入连接到噪声检测单元的输出，并且响应于检测到噪声检测的输出处的信号变化而产生对该信号的校正 单元。 控制单元具有输入和输出，其中控制单元的输入连接到信号，并且如果在信号中检测到状态改变则关闭噪声抑制单元。

    SYSTEM AND METHOD OF SELECTIVE ROW ENERGIZATION BASED ON WRITE DATA
    6.
    发明申请
    SYSTEM AND METHOD OF SELECTIVE ROW ENERGIZATION BASED ON WRITE DATA 失效
    基于写数据选择能量的系统和方法

    公开(公告)号：US20080219063A1

    公开(公告)日：2008-09-11

    申请号：US12125875

    申请日：2008-05-22

    申请人： Michael J. Lee ,  Jose A. Paredes ,  Peter J. Klim ,  Sam G. Chu

    发明人： Michael J. Lee ,  Jose A. Paredes ,  Peter J. Klim ,  Sam G. Chu

    IPC分类号： G11C7/00 ,  G11C8/00

    CPC分类号： G11C8/10

    摘要： A system and method of selective row energization based on write data, with a selective row energization system including a storage array 102 having M rows 104 and N columns 106; an N-bit data word register 108; a uniform-detect circuit 110 responsive to a data word to generate a uniform word data bit having a first value when the data word is uniform; an M-bit uniform-detect register 112 having M uniform-detect latches 114, each being associated with one of the M rows 104 and storing the uniform word data bit for the data word stored in the associated M row 104; and an M-bit row driver device 116 responsive to the uniform word data bit for each of the M rows 104 to inhibit energization of the M rows 104 for which the uniform word data bit is the first value.

    摘要翻译： 一种基于写入数据的选择性行激励的系统和方法，具有包括具有M行104和N列106的存储阵列102的选择行激励系统; N位数据字寄存器108; 均衡检测电路110响应于数据字以在数据字均匀时产生具有第一值的均匀字数据位; 具有M个均匀检测锁存器114的M位均匀检测寄存器112，每个均衡检测锁存器114与M行104中的一个相关联，并存储用于存储在相关联的M行104中的数据字的统一字数据位; 以及响应于M行104中的每一个的均匀字数据位的M位行驱动器设备116，以禁止均匀字数据位为第一值的M行104的通电。

    HIGH-SPEED LOW-POWER INTEGRATED CIRCUIT INTERCONNECTS
    7.
    发明申请
    HIGH-SPEED LOW-POWER INTEGRATED CIRCUIT INTERCONNECTS 失效
    高速低功耗集成电路互连

    公开(公告)号：US20070279097A1

    公开(公告)日：2007-12-06

    申请号：US11421457

    申请日：2006-05-31

    申请人： Zhibin Cheng ,  Satyajit Dutta ,  Peter J. Klim

    发明人： Zhibin Cheng ,  Satyajit Dutta ,  Peter J. Klim

    IPC分类号： H03K19/094

    CPC分类号： H03K19/018585 ,  H03K19/0013

    摘要： Methods and apparatuses to decrease power consumption of interconnecting devices in integrated circuits are disclosed. Embodiments comprise a method to reduce power consumption in integrated circuits by generating full and reduced swing signals at an output of a driver module in response to a control signal during and deactivating one or more elements to conserve power after an input signal remains unchanged for a period of time. Another embodiment comprises an apparatus to reduce power consumption in a circuit, the embodiment comprising a swing module coupled with a swing selector and an output controller. The swing module may generate full or low swing signals depending on the state of the swing selector. The output controller may increase the output impedance of the swing module after an input signal to the swing module remains unchanged for a quantity of time. Various apparatus embodiments include portable computing devices and cellular telephones.

    摘要翻译： 公开了降低集成电路中互连装置的功耗的方法和装置。 实施例包括一种通过在驱动器模块的输出处响应于在一个或多个元件期间的控制信号和在激活一个或多个元件以节省功率以在输入信号保持不变一段时间之后在驱动器模块的输出处产生完全和减小的摆动信号来降低集成电路中的功耗 的时间。 另一个实施例包括一种降低电路功耗的装置，该实施例包括与摆动选择器和输出控制器耦合的摆动模块。 摆动模块可以根据摆动选择器的状态产生满摆幅或低摆动信号。 输出控制器可以在摆动模块的输入信号保持不变一段时间之后增加摆动模块的输出阻抗。 各种设备实施例包括便携式计算设备和蜂窝电话。

    Computer system having a selectable memory module presence detect information option
    8.
    发明授权
    Computer system having a selectable memory module presence detect information option 失效
    具有可选存储器模块存在检测信息选项的计算机系统

    公开(公告)号：US5539912A

    公开(公告)日：1996-07-23

    申请号：US279308

    申请日：1994-07-22

    申请人： Grant L. Clarke, Jr. ,  Peter J. Klim ,  Mark G. Noll ,  Jose A. Olive

    发明人： Grant L. Clarke, Jr. ,  Peter J. Klim ,  Mark G. Noll ,  Jose A. Olive

    IPC分类号： G06F12/06 ,  G06F13/42 ,  G06F13/00

    CPC分类号： G06F13/4243 ,  G06F12/0684

    摘要： A personal computer has two possible memory sizes differing by the maximum number SIMMs that can be installed. Each SIMM stores presence detect bits indicating the size and speed of the SIMM. An I/O controller includes a memory detect port which is used to read the presence detect bits from the SIMMs. The controller further includes a logic circuit that is set in accordance with the memory size to selectively control driving the presence detect bits or empty socket bits onto a data bus.

    摘要翻译： 个人计算机有两种可能的存储容量大小，可以通过最大数量的SIMM来安装。 每个SIMM存储指示SIMM的大小和速度的存在检测位。 I / O控制器包括用于从SIMM读取存在检测位的存储器检测端口。 控制器还包括根据存储器大小设置的逻辑电路，以选择性地控制将存在检测位或空插座位驱动到数据总线上。

    High performance, low power, dynamically latched up/down counter
    10.
    发明授权
    High performance, low power, dynamically latched up/down counter 失效
    高性能，低功耗，动态锁存上/下计数器

    公开(公告)号：US07587020B2

    公开(公告)日：2009-09-08

    申请号：US11739756

    申请日：2007-04-25

    申请人： Jethro C. Law ,  Trong V. Luong ,  Hung C. Ngo ,  Peter J. Klim

    发明人： Jethro C. Law ,  Trong V. Luong ,  Hung C. Ngo ,  Peter J. Klim

    IPC分类号： H03K25/00 ,  H03K23/50

    CPC分类号： H03K23/40 ,  H03K21/026

    摘要： A high performance, low power up/down counter is set forth. The counter presented is controlled by two clock pulses, an up pulse and a down pulse, and updates all bits of the counter in parallel. These bits are then latched using a scannable pulsed limited output switching dynamic logic latch. By using a limited switch dynamic logic latch, the counter is able to utilize the speed of dynamic logic without requiring the traditional dynamic logic power. The area saved and speed gained by using a dynamic latch is significant compared to a typical edge-triggered flip-flop. Additionally, by computing all the next count state bits in parallel, the counter reduces an overall count computation delay by eliminating the counter ripple.

    摘要翻译： 提出了一个高性能，低功耗的上/下计数器。 提供的计数器由两个时钟脉冲，上升脉冲和下降脉冲控制，并并行更新计数器的所有位。 然后使用可扫描的脉冲限制输出开关动态逻辑锁存器锁存这些位。 通过使用有限开关动态逻辑锁存器，计数器能够利用动态逻辑的速度，而不需要传统的动态逻辑电源。 与典型的边沿触发触发器相比，通过使用动态锁存器保存的区域和速度是显着的。 此外，通过并行计算所有下一个计数状态位，计数器通过消除计数器纹波来减少总计数计算延迟。