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    Plasma Etched Catalytic Laminate with Traces and Vias
    2.
    发明申请
    Plasma Etched Catalytic Laminate with Traces and Vias 审中-公开

    公开(公告)号：US20190014666A1

    公开(公告)日：2019-01-10

    申请号：US15645957

    申请日：2017-07-10

    Applicant: Sierra Circuits, Inc.

    Inventor： Kenneth S. BAHL ,  Konstantine KARAVAKIS

    IPC: H05K3/02 ,  H05K3/00 ,  H05K3/06 ,  C08K3/34 ,  C08K3/36 ,  H05K3/42

    Abstract: A circuit board is formed from a catalytic laminate having a resin rich surface with catalytic particles dispersed below a surface exclusion depth. The catalytic laminate is subjected to a drilling and blanket surface plasma etch operation to expose the catalytic particles, followed by an electroless plating operation which deposits a thin layer of conductive material on the surface. A photo-masking step follows to define circuit traces, after which an electro-plating deposition occurs, followed by a resist strip operation and a quick etch to remove electroless copper which was previously covered by photoresist.

    WAFER LEVEL PACKAGING USING A CATALYTIC ADHESIVE
    3.
    发明申请
    WAFER LEVEL PACKAGING USING A CATALYTIC ADHESIVE 审中-公开
    使用催化粘合剂的水平包装

    公开(公告)号：US20160148893A1

    公开(公告)日：2016-05-26

    申请号：US15009386

    申请日：2016-01-28

    Applicant: SIERRA CIRCUITS, INC.

    Inventor： Kenneth S. Bahl ,  Konstantine Karavakis

    IPC: H01L23/00

    Abstract: Wafer level packaging includes a first layer of a catalytic adhesive on a wafer surface. The catalytic adhesive includes catalytic particles that will reduce electroless copper (Cu) from Cu++ to Cu. Metal traces are formed in trace channels within the first layer of catalytic adhesive. The trace channels extend below a surface of the first layer of the catalytic material. The trace metals traces are also in contact with integrated circuit pads on the surface of the wafer.

    Abstract translation: 晶片级封装包括在晶片表面上的第一层催化粘合剂。 催化粘合剂包括将从Cu ++减少到Cu的无电解铜（Cu）的催化颗粒。 在第一层催化粘合剂内的痕迹通道中形成金属痕迹。 迹线通道在催化材料的第一层的表面下方延伸。 微量金属迹线也与晶片表面上的集成电路焊盘接触。

    Catalytic laminate with conductive traces formed during lamination
    6.
    发明授权
    Catalytic laminate with conductive traces formed during lamination 有权

    公开(公告)号：US10827624B2

    公开(公告)日：2020-11-03

    申请号：US15911515

    申请日：2018-03-05

    Applicant: Sierra Circuits, Inc.

    Inventor： Kenneth S Bahl ,  Konstantine Karavakis

    IPC: H05K3/00 ,  H05K3/18 ,  C23C18/16 ,  C23C18/20 ,  C23C18/38 ,  H05K3/40 ,  H05K1/09 ,  H05K1/11 ,  H05K3/46 ,  H05K3/10

    Abstract: A circuit board is formed from a catalytic laminate having a resin rich surface with catalytic particles dispersed below a surface exclusion depth. Trace channels and apertures are formed into the catalytic laminate, electroless plated with a metal such as copper, filled with a conductive paste containing metallic particles, which are then melted to form traces. In a variation, multiple circuit board layers have channels formed into the surface below the exclusion depth, apertures formed, are electroless plated, and the channels and apertures filled with metal particles. Several such catalytic laminate layers are placed together and pressed together under elevated temperature until the catalytic laminate layers laminate together and metal particles form into traces for a multi-layer circuit board.

    Process for printed circuit boards using backing foil
    7.
    发明授权
    Process for printed circuit boards using backing foil 有权

    公开(公告)号：US10765012B2

    公开(公告)日：2020-09-01

    申请号：US15645921

    申请日：2017-07-10

    Applicant: Sierra Circuits, Inc.

    Inventor： Kenneth S. Bahl ,  Konstantine Karavakis

    IPC: H05K3/42 ,  H05K3/00 ,  H05K3/06 ,  H05K3/46

    Abstract: A method for making a circuit board uses a dielectric core, and at least one thin foil bottom surface with a foil backing of sufficient thickness to absorb heat from a laser drilling operation to prevent the penetration of the thin foil bottom surface during laser drilling. A sequence of steps including a laser drilling step, removing the foil backing step, electroless plating step, patterned resist step, electroplating step, resist strip step, tin plate step, and copper etch step are performed, which provide dot vias of fine linewidth and resolution.

    Circuit board with catalytic adhesive
    8.
    发明授权
    Circuit board with catalytic adhesive 有权

    公开(公告)号：US10306756B2

    公开(公告)日：2019-05-28

    申请号：US15878398

    申请日：2018-01-23

    Applicant: Sierra Circuits, Inc.

    Inventor： Kenneth S. Bahl ,  Konstantine Karavakis

    IPC: H05K1/09 ,  H05K3/38 ,  H05K1/03 ,  H05K1/02 ,  H05K3/42 ,  H05K3/46 ,  H05K1/11 ,  H05K3/18

    Abstract: A catalytic resin is formed by mixing a resin and either homogeneous or heterogeneous catalytic particles, the resin infused into a woven glass fabric to form an A-stage pre-preg, the A-stage pre-preg cured into a B-stage pre-preg, thereafter held in a vacuum and between pressure plates at a gel point temperature for a duration of time sufficient for the catalytic particles to migrate away from the resin rich surfaces of the pre-preg, thereby forming a C-stage pre-preg after cooling. The C-stage pre-preg subsequently has trenches formed by removing the resin rich surface, the trenches extending into the depth of the catalytic particles, optionally including drilled holes to form vias, and the C-stage pre-preg with trenches and holes placed in an electroless bath, whereby traces form in the trenches and holes where the surface of the cured pre-preg has been removed.

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