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公开(公告)号：US20240365468A1
公开(公告)日：2024-10-31
申请号：US18643279
申请日：2024-04-23
Applicant: IBIDEN CO., LTD.
Inventor： Masashi KUWABARA , Susumu KAGOHASHI , Jun SAKAI , Kyohei YOSHIKAWA
CPC classification number: H05K1/115 , H05K1/0306 , H05K1/113 , H05K2201/0209 , H05K2201/0242 , H05K2201/0266 , H05K2201/09536 , H05K2201/09827
Abstract: A wiring substrate includes a first build-up part including an insulating layer and a conductor layer, and a second build-up part laminated on the first build-up part and including an insulating layer and a conductor layer. The minimum width and minimum inter-wiring distance of wirings in the first build-up part are smaller than the minimum width and minimum inter-wiring distance of wirings in the second build-up part. The insulating layer in the first build-up part includes resin and inorganic particles including first inorganic particles partially embedded in the resin and second inorganic particles completely embedded in the resin such that the first inorganic particles have first portions protruding from the resin and second portions embedded in the resin, respectively. The insulating layer of the first build-up part has a surface covered by the conductor layer and including a surface of the resin and exposed surfaces of the first portions.
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公开(公告)号：US20240237204A1
公开(公告)日：2024-07-11
申请号：US18408629
申请日：2024-01-10
Applicant: IBIDEN CO., LTD.
Inventor： Keisuke SHIMIZU , Fumio NISHIWAKI , Ryoya KIMURA
IPC: H05K1/02
CPC classification number: H05K1/0298 , H05K2201/0209 , H05K2201/0242
Abstract: A wiring substrate includes a first wiring part including a first insulating layer and a first conductor layer laminated on the first insulating layer, and a second wiring part including a second insulating layer and a second conductor layer laminated on the second insulating layer. The thickness of the second insulating layer is smaller than that of the first insulating layer. The thickness of the second conductor layer is smaller than that of the first conductor layer. The first conductor layer includes first wirings including differential wirings having the minimum wiring width of larger than 5 μm and minimum inter-wiring distance of larger than 7 μm. The second conductor layer includes second wirings having the maximum wiring width of 5 μm or less and the maximum inter-wiring distance of 7 μm or less. The second part is positioned closer to the outermost surface of the substrate than the first part.
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公开(公告)号：US20190239349A1
公开(公告)日：2019-08-01
申请号：US16381823
申请日：2019-04-11
Applicant: Sierra Circuits, Inc.
Inventor： Kenneth S. BAHL , Konstantine KARAVAKIS
CPC classification number: H05K1/0313 , H05K1/0296 , H05K1/0353 , H05K1/0366 , H05K1/0373 , H05K1/038 , H05K1/09 , H05K1/115 , H05K3/18 , H05K3/181 , H05K3/182 , H05K3/387 , H05K3/422 , H05K3/429 , H05K3/4632 , H05K2201/0209 , H05K2201/0227 , H05K2201/0242 , H05K2201/0376 , H05K2203/0716
Abstract: A catalytic resin is formed by mixing a resin and either homogeneous or heterogeneous catalytic particles, the resin infused into a woven glass fabric to form an A-stage pre-preg, the A-stage pre-preg cured into a B-stage pre-preg, thereafter held in a vacuum and between pressure plates at a gel point temperature for a duration of time sufficient for the catalytic particles to migrate away from the resin rich surfaces of the pre-preg, thereby forming a C-stage pre-preg after cooling. The C-stage pre-preg subsequently has trenches formed by removing the resin rich surface, the trenches extending into the depth of the catalytic particles, optionally including drilled holes to form vias, and the C-stage pre-preg with trenches and holes placed in an electroless bath, whereby traces form in the trenches and holes where the surface of the cured pre-preg has been removed.
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公开(公告)号：US20180054889A1
公开(公告)日：2018-02-22
申请号：US15603326
申请日：2017-05-23
Applicant: Sierra Circuits, Inc.
Inventor： Kenneth S. BAHL , Konstantine KARAVAKIS
CPC classification number: H05K1/0313 , H05K1/0296 , H05K1/0353 , H05K1/0366 , H05K1/0373 , H05K1/038 , H05K1/09 , H05K1/115 , H05K3/18 , H05K3/181 , H05K3/182 , H05K3/387 , H05K3/422 , H05K3/429 , H05K3/4632 , H05K2201/0209 , H05K2201/0227 , H05K2201/0242 , H05K2201/0376 , H05K2203/0716
Abstract: A catalytic resin is formed by mixing a resin and either homogeneous or heterogeneous catalytic particles, the resin infused into a woven glass fabric to form an A-stage pre-preg, the A-stage pre-preg cured into a B-stage pre-preg, thereafter held in a vacuum and between pressure plates at a gel point temperature for a duration of time sufficient for the catalytic particles to migrate away from the resin rich surfaces of the pre-preg, thereby forming a C-stage pre-preg after cooling. The C-stage pre-preg subsequently has trenches formed by removing the resin rich surface, the trenches extending into the depth of the catalytic particles, optionally including drilled holes to form vias, and the C-stage pre-preg with trenches and holes placed in an electroless bath, whereby traces form in the trenches and holes where the surface of the cured pre-preg has been removed.
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5.发明申请公开(公告)号：US20170298218A1
公开(公告)日：2017-10-19
申请号：US15318787
申请日：2016-09-08
Applicant: SHENGYI TECHNOLOGY CO., LTD.
Inventor： Hui LI , Kehong FANG , Yongjing XU
IPC: C08L63/00 , C08G59/50 , C08G59/62 , C08J5/04 , C08G59/42 , H01B3/40 , C08L63/08 , C08J5/24 , H05K1/03
CPC classification number: C08L63/00 , B32B5/022 , B32B5/024 , B32B5/26 , B32B7/04 , B32B15/06 , B32B15/092 , B32B15/14 , B32B15/20 , B32B25/02 , B32B25/042 , B32B27/08 , B32B27/20 , B32B27/26 , B32B27/28 , B32B27/281 , B32B27/285 , B32B27/302 , B32B27/32 , B32B27/325 , B32B27/34 , B32B27/36 , B32B27/38 , B32B27/42 , B32B2250/05 , B32B2255/02 , B32B2255/10 , B32B2255/205 , B32B2260/023 , B32B2260/046 , B32B2262/101 , B32B2264/0214 , B32B2264/0257 , B32B2264/10 , B32B2264/102 , B32B2264/104 , B32B2264/107 , B32B2264/12 , B32B2270/00 , B32B2307/204 , B32B2307/21 , B32B2307/302 , B32B2307/306 , B32B2307/3065 , B32B2307/308 , B32B2307/4026 , B32B2307/724 , B32B2307/748 , B32B2457/08 , C08G14/06 , C08G59/40 , C08G59/42 , C08G59/4238 , C08G59/4284 , C08G59/5046 , C08G59/621 , C08G73/0233 , C08G73/06 , C08J5/043 , C08J5/24 , C08J2363/00 , C08J2363/02 , C08J2363/08 , C08K3/01 , C08K5/0025 , C08K13/02 , C08L35/06 , C08L61/34 , C08L63/08 , C08L79/04 , C08L2201/02 , C08L2201/22 , C08L2203/20 , C08L2205/02 , C08L2205/05 , H01B3/40 , H05K1/0326 , H05K1/0346 , H05K1/0366 , H05K1/0373 , H05K2201/012 , H05K2201/0209 , H05K2201/0212 , H05K2201/0242
Abstract: The present invention relates to a halogen-free epoxy resin composition, a prepreg, a laminate and a printed circuit board containing the same. The halogen-free epoxy resin composition comprises an epoxy resin and a curing agent. Taking the total equivalent amount of the epoxy groups in the epoxy resin as 1, the active groups in the curing agent which react with the epoxy groups have an equivalent amount of 0.5-0.95. By controlling the equivalent ratio of the epoxy groups in the epoxy resin to the active groups in the curing agent to be 0.5-0.95, the present invention ensures the Df value stability of prepregs under different curing temperature conditions while maintaining a low dielectric constant and a low dielectric loss. The prepregs and laminates prepared from the resin composition have comprehensive performances, such as low dielectric constant, low dielectric loss, excellent flame retardancy, heat resistance, cohesiveness, low water absorption and moisture resistance, and are suitable for use in halogen-free multilayer circuit boards.
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Patent Agency Ranking
公开(公告)号：US09392701B2
公开(公告)日：2016-07-12
申请号：US14289932
申请日：2014-05-29
Applicant: SAE Magnetics (H.K.) Ltd.
Inventor： Akio Nakao , Hidenobu Takemoto
CPC classification number: H05K3/284 , H01L2924/3025 , H05K1/0216 , H05K9/0024 , H05K9/0045 , H05K2201/0209 , H05K2201/0242 , H05K2201/2072
Abstract: An electronic component package includes a substrate having at least one electronic circuit; a sealing resin for sealing the electronic circuit, at least one filler on which at least one crack is formed being filled in the sealing; and a metal film formed on a top surface of the sealing resin, a root of the metal film being embedded in the crack on the filler. The electronic component package can shield the environmental electromagnetic noise and satisfy with lightweight requirement for the integrated circuit modules.
Abstract translation: 电子部件封装包括具有至少一个电子电路的基板; 用于密封电子电路的密封树脂，至少一个其上形成有至少一个裂纹的填料被填充在密封中; 以及形成在密封树脂的顶表面上的金属膜，金属膜的根部嵌入在填料上的裂纹中。 电子元件封装可以屏蔽环境电磁噪声，满足集成电路模块的轻量化要求。
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公开(公告)号：US20240324103A1
公开(公告)日：2024-09-26
申请号：US18613202
申请日：2024-03-22
Applicant: IBIDEN CO., LTD.
Inventor： Masashi KUWABARA , Jun SAKAI , Shiho FUKUSHIMA
CPC classification number: H05K1/115 , H05K1/0306 , H05K3/16 , H05K2201/0209 , H05K2201/0242 , H05K2201/0266 , H05K2201/032 , H05K2201/09536
Abstract: A wiring substrate includes a core substrate including a through-hole conductor, a first resin insulating layer, a first conductor layer including a seed layer and an electrolytic plating layer, a via conductor formed such that the via conductor electrically connects the through-hole conductor and first conductor layer, and a second resin insulating layer covering the first conductor layer. The core substrate includes a glass substrate such that the through-hole conductor is penetrating through the glass substrate, the seed layer includes a first layer formed on the first resin insulating layer and a second layer formed on the first layer, and the first conductor layer includes a conductor circuit such that a width of the first layer is larger than a width of the second layer in the conductor circuit and a width of the electrolytic plating layer is larger than the width of the first layer in the conductor circuit.
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公开(公告)号：US11763959B2
公开(公告)日：2023-09-19
申请号：US17289023
申请日：2019-10-23
Applicant: TSE CO., LTD.
Inventor： Chang Su Oh , Bo Hyun Kim , Sung Ho Yoon
CPC classification number: H01B5/00 , H05K1/115 , H05K3/10 , H05K1/092 , H05K3/0014 , H05K2201/0242 , H05K2201/0263 , H05K2203/104
Abstract: The purpose of the present disclosure is to provide electro-conductive particles and a signal-transmitting connector having same, wherein the electro-conductive particles are improved to prevent the phenomenon of irregular scrub between the electro-conductive particles and to have improved signal delivery characteristics. Electro-conductive particles according to the present disclosure are provided on a signal-transmitting connector having multiple electroconductive portions supported by an insulating portion made of an elastic insulating material to be spaced apart from each other such that the signal-transmitting connector can be connected to an electronic component and can transmit electric signals.
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公开(公告)号：US09942981B2
公开(公告)日：2018-04-10
申请号：US15603326
申请日：2017-05-23
Applicant: Sierra Circuits, Inc.
Inventor： Kenneth S. Bahl , Konstantine Karavakis
IPC: H05K1/03 , H05K3/00 , H05K3/18 , H05K3/38 , H05K3/42 , H05K1/11 , H05K3/46 , H05K1/09 , H05K1/02
CPC classification number: H05K1/0313 , H05K1/0296 , H05K1/0353 , H05K1/0366 , H05K1/0373 , H05K1/038 , H05K1/09 , H05K1/115 , H05K3/18 , H05K3/181 , H05K3/182 , H05K3/387 , H05K3/422 , H05K3/429 , H05K3/4632 , H05K2201/0209 , H05K2201/0227 , H05K2201/0242 , H05K2201/0376 , H05K2203/0716
Abstract: A catalytic resin is formed by mixing a resin and either homogeneous or heterogeneous catalytic particles, the resin infused into a woven glass fabric to form an A-stage pre-preg, the A-stage pre-preg cured into a B-stage pre-preg, thereafter held in a vacuum and between pressure plates at a gel point temperature for a duration of time sufficient for the catalytic particles to migrate away from the resin rich surfaces of the pre-preg, thereby forming a C-stage pre-preg after cooling. The C-stage pre-preg subsequently has trenches formed by removing the resin rich surface, the trenches extending into the depth of the catalytic particles, optionally including drilled holes to form vias, and the C-stage pre-preg with trenches and holes placed in an electroless bath, whereby traces form in the trenches and holes where the surface of the cured pre-preg has been removed.
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公开(公告)号：US20150124417A1
公开(公告)日：2015-05-07
申请号：US14289932
申请日：2014-05-29
Applicant: SAE Magnetics (H.K.) Ltd.
Inventor： Akio NAKAO , Hidenobu TAKEMOTO
IPC: H05K1/18
CPC classification number: H05K3/284 , H01L2924/3025 , H05K1/0216 , H05K9/0024 , H05K9/0045 , H05K2201/0209 , H05K2201/0242 , H05K2201/2072
Abstract: An electronic component package includes a substrate having at least one electronic circuit; a sealing resin for sealing the electronic circuit, at least one filler on which at least one crack is formed being filled in the sealing; and a metal film formed on a top surface of the sealing resin, a root of the metal film being embedded in the crack on the filler. The electronic component package can shield the environmental electromagnetic noise and satisfy with lightweight requirement for the integrated circuit modules.
Abstract translation: 电子部件封装包括具有至少一个电子电路的基板; 用于密封电子电路的密封树脂，至少一个其上形成有至少一个裂纹的填料被填充在密封中; 以及形成在密封树脂的顶表面上的金属膜，金属膜的根部嵌入在填料上的裂纹中。 电子元件封装可以屏蔽环境电磁噪声，满足集成电路模块的轻量化要求。
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