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公开(公告)号：US20180168036A1
公开(公告)日：2018-06-14
申请号：US15878398
申请日：2018-01-23
Applicant: Sierra Circuits, Inc.
Inventor： Kenneth S. BAHL , Konstantine KARAVAKIS
CPC classification number: H05K1/0313 , H05K1/0296 , H05K1/0353 , H05K1/0366 , H05K1/0373 , H05K1/038 , H05K1/09 , H05K1/115 , H05K3/18 , H05K3/181 , H05K3/182 , H05K3/387 , H05K3/422 , H05K3/429 , H05K3/4632 , H05K2201/0209 , H05K2201/0227 , H05K2201/0242 , H05K2201/0376 , H05K2203/0716
Abstract: A catalytic resin is formed by mixing a resin and either homogeneous or heterogeneous catalytic particles, the resin infused into a woven glass fabric to form an A-stage pre-preg, the A-stage pre-preg cured into a B-stage pre-preg, thereafter held in a vacuum and between pressure plates at a gel point temperature for a duration of time sufficient for the catalytic particles to migrate away from the resin rich surfaces of the pre-preg, thereby forming a C-stage pre-preg after cooling. The C-stage pre-preg subsequently has trenches formed by removing the resin rich surface, the trenches extending into the depth of the catalytic particles, optionally including drilled holes to form vias, and the C-stage pre-preg with trenches and holes placed in an electroless bath, whereby traces form in the trenches and holes where the surface of the cured pre-preg has been removed.
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公开(公告)号：US20190239349A1
公开(公告)日：2019-08-01
申请号：US16381823
申请日：2019-04-11
Applicant: Sierra Circuits, Inc.
Inventor： Kenneth S. BAHL , Konstantine KARAVAKIS
CPC classification number: H05K1/0313 , H05K1/0296 , H05K1/0353 , H05K1/0366 , H05K1/0373 , H05K1/038 , H05K1/09 , H05K1/115 , H05K3/18 , H05K3/181 , H05K3/182 , H05K3/387 , H05K3/422 , H05K3/429 , H05K3/4632 , H05K2201/0209 , H05K2201/0227 , H05K2201/0242 , H05K2201/0376 , H05K2203/0716
Abstract: A catalytic resin is formed by mixing a resin and either homogeneous or heterogeneous catalytic particles, the resin infused into a woven glass fabric to form an A-stage pre-preg, the A-stage pre-preg cured into a B-stage pre-preg, thereafter held in a vacuum and between pressure plates at a gel point temperature for a duration of time sufficient for the catalytic particles to migrate away from the resin rich surfaces of the pre-preg, thereby forming a C-stage pre-preg after cooling. The C-stage pre-preg subsequently has trenches formed by removing the resin rich surface, the trenches extending into the depth of the catalytic particles, optionally including drilled holes to form vias, and the C-stage pre-preg with trenches and holes placed in an electroless bath, whereby traces form in the trenches and holes where the surface of the cured pre-preg has been removed.
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公开(公告)号：US20190014666A1
公开(公告)日：2019-01-10
申请号：US15645957
申请日：2017-07-10
Applicant: Sierra Circuits, Inc.
Inventor： Kenneth S. BAHL , Konstantine KARAVAKIS
Abstract: A circuit board is formed from a catalytic laminate having a resin rich surface with catalytic particles dispersed below a surface exclusion depth. The catalytic laminate is subjected to a drilling and blanket surface plasma etch operation to expose the catalytic particles, followed by an electroless plating operation which deposits a thin layer of conductive material on the surface. A photo-masking step follows to define circuit traces, after which an electro-plating deposition occurs, followed by a resist strip operation and a quick etch to remove electroless copper which was previously covered by photoresist.
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公开(公告)号：US20190274221A1
公开(公告)日：2019-09-05
申请号：US15911515
申请日：2018-03-05
Applicant: Sierra Circuits, Inc.
Inventor： Kenneth S BAHL , Konstantine KARAVAKIS
IPC: H05K3/18 , C23C18/16 , C23C18/20 , C23C18/38 , H05K3/40 , H05K3/00 , H05K3/10 , H05K1/09 , H05K1/11 , H05K3/46
Abstract: A circuit board is formed from a catalytic laminate having a resin rich surface with catalytic particles dispersed below a surface exclusion depth. Trace channels and apertures are formed into the catalytic laminate, electroless plated with a metal such as copper, filled with a conductive paste containing metallic particles, which are then melted to form traces. In a variation, multiple circuit board layers have channels formed into the surface below the exclusion depth, apertures formed, are electroless plated, and the channels and apertures filled with metal particles. Several such catalytic laminate layers are placed together and pressed together under elevated temperature until the catalytic laminate layers laminate together and metal particles form into traces for a multi-layer circuit board.
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Patent Agency Ranking
公开(公告)号：US20200008306A1
公开(公告)日：2020-01-02
申请号：US16024835
申请日：2018-06-30
Applicant: Sierra Circuits, Inc.
Inventor： Konstantine KARAVAKIS , Kenneth BAHL , Steve Carney
Abstract: A circuit board is formed from a non-catalytic laminate coated with an optically curable catalytic adhesive, which, after curing with an optical source such as UV, has a resin rich surface with catalytic particles dispersed below a surface exclusion depth. The catalytic laminate is subjected to a drilling and blanket surface plasma etch operation to expose the catalytic particles, followed by an electroless plating operation which deposits a thin layer of conductive material on the surface. A photo-masking step follows to define circuit traces, after which an electro-plating deposition occurs, followed by a resist strip operation and a quick etch to remove electroless copper which was previously covered by photoresist.
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公开(公告)号：US20190014667A1
公开(公告)日：2019-01-10
申请号：US15645921
申请日：2017-07-10
Applicant: Sierra Circuits, Inc.
Inventor： Kenneth S. BAHL , Konstantine KARAVAKIS
Abstract: A circuit board has a dielectric core, a foil top surface, and a thin foil bottom surface with a foil backing of sufficient thickness to absorb heat from a laser drilling operation to prevent the penetration of the thin foil bottom surface during laser drilling. A sequence of steps including a laser drilling step, removing the foil backing step, electroless plating step, patterned resist step, electroplating step, resist strip step, tin plate step, and copper etch step are performed, which provide dot vias of fine linewidth and resolution.
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公开(公告)号：US20190008044A1
公开(公告)日：2019-01-03
申请号：US15635201
申请日：2017-06-28
Applicant: Sierra Circuits, Inc.
Inventor： Konstantine KARAVAKIS , Kenneth S. BAHL
CPC classification number: H05K1/115 , H05K1/0313 , H05K1/095 , H05K1/111 , H05K3/06 , H05K3/181 , H05K3/425 , H05K3/462 , H05K3/4623 , H05K2201/09572 , H05K2201/10378 , H05K2203/068 , H05K2203/085
Abstract: A multi-layer circuit board is formed by positioning a top sub having traces on at least one side to one or more pairs of composite layers, each composite layer comprising an interposer layer and a sub layer. Each sub layer which is adjacent to an interposer layer having an interconnection aperture, the interconnection aperture positioned adjacent to interconnections having a plated through via or pad on each corresponding sub layer. Each interposer aperture is filled with a conductive paste, and the stack of top sub and one or more pairs of composite layers are placed into a lamination press, the enclosure evacuated, and an elevated temperature and laminated pressure is applied until the conductive paste has melted, connecting the adjacent interconnections, and the boards are laminated together into completed laminated multi-layer circuit board.
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8.发明申请公开(公告)号：US20180158793A1
公开(公告)日：2018-06-07
申请号：US15889017
申请日：2018-02-05
Applicant: Sierra Circuits, Inc.
Inventor： Kenneth S. BAHL , Konstantine KARAVAKIS
IPC: H01L23/00 , H01L21/56 , H01L23/498 , H01L21/48
Abstract: A catalytic laminate is formed from a resin, a fiber reinforced layer, and catalytic particles such that the catalytic particles are disposed throughout the catalytic laminate but excluded from the outer surface of the catalytic laminate. The catalytic laminate has trace channels and vias formed to make a single or multi-layer catalytic laminate printed circuit board. Apertures with locations which match the locations of integrated circuit pads are formed in the laminate PCB. The integrated circuit is bonded to the catalytic laminate PCB, and the integrated circuit and laminate are both subjected to electroless plating, thereby electrically connecting the integrated circuit to the single or multi-layer catalytic laminate PCB.
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公开(公告)号：US20180054889A1
公开(公告)日：2018-02-22
申请号：US15603326
申请日：2017-05-23
Applicant: Sierra Circuits, Inc.
Inventor： Kenneth S. BAHL , Konstantine KARAVAKIS
CPC classification number: H05K1/0313 , H05K1/0296 , H05K1/0353 , H05K1/0366 , H05K1/0373 , H05K1/038 , H05K1/09 , H05K1/115 , H05K3/18 , H05K3/181 , H05K3/182 , H05K3/387 , H05K3/422 , H05K3/429 , H05K3/4632 , H05K2201/0209 , H05K2201/0227 , H05K2201/0242 , H05K2201/0376 , H05K2203/0716
Abstract: A catalytic resin is formed by mixing a resin and either homogeneous or heterogeneous catalytic particles, the resin infused into a woven glass fabric to form an A-stage pre-preg, the A-stage pre-preg cured into a B-stage pre-preg, thereafter held in a vacuum and between pressure plates at a gel point temperature for a duration of time sufficient for the catalytic particles to migrate away from the resin rich surfaces of the pre-preg, thereby forming a C-stage pre-preg after cooling. The C-stage pre-preg subsequently has trenches formed by removing the resin rich surface, the trenches extending into the depth of the catalytic particles, optionally including drilled holes to form vias, and the C-stage pre-preg with trenches and holes placed in an electroless bath, whereby traces form in the trenches and holes where the surface of the cured pre-preg has been removed.
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