公开(公告)号：US20160148893A1

公开(公告)日：2016-05-26

申请号：US15009386

申请日：2016-01-28

Applicant: SIERRA CIRCUITS, INC.

Inventor： Kenneth S. Bahl ,  Konstantine Karavakis

IPC: H01L23/00

Abstract: Wafer level packaging includes a first layer of a catalytic adhesive on a wafer surface. The catalytic adhesive includes catalytic particles that will reduce electroless copper (Cu) from Cu++ to Cu. Metal traces are formed in trace channels within the first layer of catalytic adhesive. The trace channels extend below a surface of the first layer of the catalytic material. The trace metals traces are also in contact with integrated circuit pads on the surface of the wafer.

Abstract translation: 晶片级封装包括在晶片表面上的第一层催化粘合剂。 催化粘合剂包括将从Cu ++减少到Cu的无电解铜（Cu）的催化颗粒。 在第一层催化粘合剂内的痕迹通道中形成金属痕迹。 迹线通道在催化材料的第一层的表面下方延伸。 微量金属迹线也与晶片表面上的集成电路焊盘接触。

公开(公告)号：US09942981B2

公开(公告)日：2018-04-10

申请号：US15603326

申请日：2017-05-23

Applicant: Sierra Circuits, Inc.

Inventor： Kenneth S. Bahl ,  Konstantine Karavakis

IPC: H05K1/03 ,  H05K3/00 ,  H05K3/18 ,  H05K3/38 ,  H05K3/42 ,  H05K1/11 ,  H05K3/46 ,  H05K1/09 ,  H05K1/02

CPC classification number: H05K1/0313 ,  H05K1/0296 ,  H05K1/0353 ,  H05K1/0366 ,  H05K1/0373 ,  H05K1/038 ,  H05K1/09 ,  H05K1/115 ,  H05K3/18 ,  H05K3/181 ,  H05K3/182 ,  H05K3/387 ,  H05K3/422 ,  H05K3/429 ,  H05K3/4632 ,  H05K2201/0209 ,  H05K2201/0227 ,  H05K2201/0242 ,  H05K2201/0376 ,  H05K2203/0716

Abstract: A catalytic resin is formed by mixing a resin and either homogeneous or heterogeneous catalytic particles, the resin infused into a woven glass fabric to form an A-stage pre-preg, the A-stage pre-preg cured into a B-stage pre-preg, thereafter held in a vacuum and between pressure plates at a gel point temperature for a duration of time sufficient for the catalytic particles to migrate away from the resin rich surfaces of the pre-preg, thereby forming a C-stage pre-preg after cooling. The C-stage pre-preg subsequently has trenches formed by removing the resin rich surface, the trenches extending into the depth of the catalytic particles, optionally including drilled holes to form vias, and the C-stage pre-preg with trenches and holes placed in an electroless bath, whereby traces form in the trenches and holes where the surface of the cured pre-preg has been removed.

公开(公告)号：US09674967B2

公开(公告)日：2017-06-06

申请号：US15184426

申请日：2016-06-16

Applicant: SIERRA CIRCUITS, INC.

Inventor： Konstantine Karavakis ,  Kenneth S. Bahl

IPC: H05K1/11 ,  H05K3/42 ,  H05K3/38 ,  H05K1/09 ,  H05K3/00

CPC classification number: H05K3/426 ,  H05K1/09 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/387 ,  H05K2201/0221 ,  H05K2201/0236 ,  H05K2203/0709 ,  Y10T29/49167

Abstract: A via in a printed circuit board is composed of a patterned metal layer that extends through a hole in dielectric laminate material that has been covered with catalytic adhesive material on both faces of the dielectric laminate material. The layer of catalytic adhesive coats a portion of the dielectric laminate material around the hole. The patterned metal layer is placed over the catalytic adhesive material on both faces of the dielectric laminate material and within the hole.

公开(公告)号：US10349520B2

公开(公告)日：2019-07-09

申请号：US15635201

申请日：2017-06-28

Applicant: Sierra Circuits, Inc.

Inventor： Konstantine Karavakis ,  Kenneth S. Bahl

IPC: H05K1/11 ,  H05K1/03 ,  H05K1/09 ,  H05K3/06 ,  H05K3/18 ,  H05K3/42 ,  H05K3/46

Abstract: A multi-layer circuit board is formed by positioning a top sub having traces on at least one side to one or more pairs of composite layers, each composite layer comprising an interposer layer and a sub layer. Each sub layer which is adjacent to an interposer layer having an interconnection aperture, the interconnection aperture positioned adjacent to interconnections having a plated through via or pad on each corresponding sub layer. Each interposer aperture is filled with a conductive paste, and the stack of top sub and one or more pairs of composite layers are placed into a lamination press, the enclosure evacuated, and an elevated temperature and laminated pressure is applied until the conductive paste has melted, connecting the adjacent interconnections, and the boards are laminated together into completed laminated multi-layer circuit board.

公开(公告)号：US09922951B1

公开(公告)日：2018-03-20

申请号：US15350019

申请日：2016-11-12

Applicant: Sierra Circuits, Inc.

Inventor： Kenneth S. Bahl ,  Konstantine Karavakis

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L24/29 ,  H01L21/486 ,  H01L21/563 ,  H01L23/49894 ,  H01L24/06 ,  H01L24/24 ,  H01L24/27 ,  H01L24/82 ,  H01L24/83 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/27464 ,  H01L2224/29147 ,  H01L2224/29553 ,  H01L2224/83639 ,  H01L2224/83644 ,  H01L2224/83647 ,  H01L2224/83655 ,  H01L2224/83657 ,  H01L2224/83678 ,  H01L2224/92144

Abstract: A catalytic laminate is formed from a resin, a fiber reinforced layer, and catalytic particles such that the catalytic particles are disposed throughout the catalytic laminate but excluded from the outer surface of the catalytic laminate. The catalytic laminate has trace channels and vias formed to make a single or multi-layer catalytic laminate printed circuit board. Apertures with locations which match the locations of integrated circuit pads are formed in the laminate PCB. The integrated circuit is bonded to the catalytic laminate PCB, and the integrated circuit and laminate are both subjected to electroless plating, thereby electrically connecting the integrated circuit to the single or multi-layer catalytic laminate PCB.

公开(公告)号：US20160295708A1

公开(公告)日：2016-10-06

申请号：US15184426

申请日：2016-06-16

Applicant: SIERRA CIRCUITS, INC.

Inventor： Konstantine Karavakis ,  Kenneth S. Bahl

IPC: H05K3/42 ,  H05K3/00 ,  H05K3/38 ,  H05K1/09 ,  H05K1/11

CPC classification number: H05K3/426 ,  H05K1/09 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/387 ,  H05K2201/0221 ,  H05K2201/0236 ,  H05K2203/0709 ,  Y10T29/49167

Abstract: A via in a printed circuit board is composed of a patterned metal layer that extends through a hole in dielectric laminate material that has been covered with catalytic adhesive material on both faces of the dielectric laminate material. The layer of catalytic adhesive coats a portion of the dielectric laminate material around the hole. The patterned metal layer is placed over the catalytic adhesive material on both faces of the dielectric laminate material and within the hole.

公开(公告)号：US20160278206A1

公开(公告)日：2016-09-22

申请号：US15165458

申请日：2016-05-26

Applicant: SIERRA CIRCUITS, INC.

Inventor： Kenneth S. Bahl ,  Konstantine Karavakis

IPC: H05K1/03 ,  H05K3/40 ,  H05K3/18 ,  H05K3/00 ,  H05K1/11 ,  H05K1/09

CPC classification number: H05K3/4038 ,  H05K1/09 ,  H05K1/115 ,  H05K3/0041 ,  H05K3/107 ,  H05K3/185 ,  H05K2201/0154 ,  H05K2201/0236 ,  H05K2201/0376 ,  H05K2203/025 ,  H05K2203/0716 ,  H05K2203/107

Abstract: A printed circuit board includes a laminate substrate. The laminate substrate includes catalytic material that resists metal plating except where a surface of the catalytic material is ablated. Metal traces are formed within in trace channels within the laminate substrate. The channels extend below the surface of the catalytic material.

Abstract translation: 印刷电路板包括层叠基板。 层压基板包括抵抗金属电镀的催化材料，除了催化材料的表面被烧蚀之外。 金属痕迹形成在层压基板内的痕迹通道内。 通道延伸到催化材料的表面之下。

公开(公告)号：US20160135297A1

公开(公告)日：2016-05-12

申请号：US15001140

申请日：2016-01-19

Applicant: SIERRA CIRCUITS, INC.

Inventor： Konstantine Karavakis ,  Kenneth S. Bahl

IPC: H05K1/11 ,  H05K3/42 ,  H05K1/09 ,  H05K3/00

CPC classification number: H05K3/387 ,  H05K3/427 ,  H05K2201/0221 ,  H05K2201/0236 ,  H05K2203/0709 ,  Y10T29/49167

Abstract: A via in a printed circuit board is composed of a patterned metal layer that extends through a hole in dielectric laminate material. A layer of catalytic adhesive coats walls within the hole. The patterned metal layer is placed over the catalytic adhesive within the hole.

Abstract translation: 印刷电路板中的通孔由延伸穿过介电层压材料中的孔的图案化金属层组成。 一层催化粘合剂涂在孔内的墙壁。 图案化金属层放置在孔内的催化粘合剂上。

公开(公告)号：US10827624B2

公开(公告)日：2020-11-03

申请号：US15911515

申请日：2018-03-05

Applicant: Sierra Circuits, Inc.

Inventor： Kenneth S Bahl ,  Konstantine Karavakis

IPC: H05K3/00 ,  H05K3/18 ,  C23C18/16 ,  C23C18/20 ,  C23C18/38 ,  H05K3/40 ,  H05K1/09 ,  H05K1/11 ,  H05K3/46 ,  H05K3/10

Abstract: A circuit board is formed from a catalytic laminate having a resin rich surface with catalytic particles dispersed below a surface exclusion depth. Trace channels and apertures are formed into the catalytic laminate, electroless plated with a metal such as copper, filled with a conductive paste containing metallic particles, which are then melted to form traces. In a variation, multiple circuit board layers have channels formed into the surface below the exclusion depth, apertures formed, are electroless plated, and the channels and apertures filled with metal particles. Several such catalytic laminate layers are placed together and pressed together under elevated temperature until the catalytic laminate layers laminate together and metal particles form into traces for a multi-layer circuit board.

公开(公告)号：US10765012B2

公开(公告)日：2020-09-01

申请号：US15645921

申请日：2017-07-10

Applicant: Sierra Circuits, Inc.

Inventor： Kenneth S. Bahl ,  Konstantine Karavakis

IPC: H05K3/42 ,  H05K3/00 ,  H05K3/06 ,  H05K3/46

Abstract: A method for making a circuit board uses a dielectric core, and at least one thin foil bottom surface with a foil backing of sufficient thickness to absorb heat from a laser drilling operation to prevent the penetration of the thin foil bottom surface during laser drilling. A sequence of steps including a laser drilling step, removing the foil backing step, electroless plating step, patterned resist step, electroplating step, resist strip step, tin plate step, and copper etch step are performed, which provide dot vias of fine linewidth and resolution.