公开(公告)号：US20080137318A1

公开(公告)日：2008-06-12

申请号：US11636250

申请日：2006-12-08

申请人： Sudarshan Rangaraj ,  Shankar Ganapathysubramanian ,  Richard Harries ,  Mitul Modi ,  Sankara J. Subramanian

发明人： Sudarshan Rangaraj ,  Shankar Ganapathysubramanian ,  Richard Harries ,  Mitul Modi ,  Sankara J. Subramanian

IPC分类号： H05K7/02 ,  H05K3/22

CPC分类号： H05K1/0271 ,  H01L23/13 ,  H01L2924/0002 ,  H05K3/3436 ,  H05K2201/0133 ,  H05K2201/0187 ,  H05K2201/068 ,  Y10T29/49158 ,  H01L2924/00

摘要： A compliant structure for an electronic device comprises a substrate (110) composed of a first material (111) and a compliant zone (120) within the substrate. A plurality of solder joints (280) are located between, and form a connection between, the substrate and the electronic device (290). The compliant zone reduces the degree of deformation experienced by the solder joints due to thermal mismatch loading between the substrate and the die during attachment of the die to the substrate (chip attach). This reduction in solder joint deformation reduces the likelihood that the solder joints will crack.

摘要翻译： 用于电子设备的柔性结构包括由衬底内的第一材料（111）和柔性区（120）组成的衬底（110）。 多个焊接接头（280）位于衬底和电子器件（290）之间，并形成衬底和电子器件（290）之间的连接。 柔性区域在将管芯附着到衬底（芯片连接）期间由于衬底和裸片之间的热失配加载而减小焊点所经历的变形程度。 焊点变形的这种减少降低了焊点会破裂的可能性。

公开(公告)号：US20080096310A1

公开(公告)日：2008-04-24

申请号：US11541233

申请日：2006-09-29

申请人： Mitul Modi ,  Sudarshan V. Rangaraj ,  Shankar Ganapathysubramanian ,  Richard J. Harries ,  Sankara J. Subramanian

发明人： Mitul Modi ,  Sudarshan V. Rangaraj ,  Shankar Ganapathysubramanian ,  Richard J. Harries ,  Sankara J. Subramanian

IPC分类号： H01L21/00 ,  H01L23/02

CPC分类号： H01L23/147 ,  H01L23/15 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/162 ,  H05K3/4644 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/068 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A linear coefficient of thermal expansion (CTE) mismatch between two materials, such as between a microelectronic die and a mounting substrate, may induce stress at the interface of the materials. The temperature changes present during the process of attaching a die to a mounting substrate can cause cracking and failure in the electrical connections used to connect the die and mounting substrate. A material with a CTE approximately matching the die CTE is introduced in the mounting substrate to reduce the stress and cracking at the electrical connections between the die and mounting substrate. Additionally, this material may comprise thin film capacitors useful for decoupling power supplies.

摘要翻译： 两种材料（例如微电子管芯和安装衬底之间）的线性热膨胀系数（CTE）失配可能在材料的界面处引起应力。 在将管芯附接到安装基板的过程中存在的温度变化可能导致用于连接管芯和安装基板的电连接中的开裂和故障。 在安装基板中引入具有与模具CTE近似匹配的CTE的材料，以减少管芯和安装基板之间的电连接处的应力和开裂。 此外，该材料可以包括用于去耦电源的薄膜电容器。

公开(公告)号：US20080001282A1

公开(公告)日：2008-01-03

申请号：US11479258

申请日：2006-06-30

申请人： Mitul Modi ,  Sudarshan V. Rangaraj ,  Shankar Ganapathysubramanian ,  Richard J. Harries ,  Sankara J. Subramanian

发明人： Mitul Modi ,  Sudarshan V. Rangaraj ,  Shankar Ganapathysubramanian ,  Richard J. Harries ,  Sankara J. Subramanian

IPC分类号： H01L23/10

CPC分类号： H01L23/42 ,  H01L21/563 ,  H01L23/10 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/26145 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/16152 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A microelectronic assembly is provided, comprising at least a first microelectronic die carrying a microelectronic circuit, at least a first periphery seal attached to an edge of a surface of the microelectronic die, at least a first solder thermal interface material attached to a central region of the surface of the microelectronic die, the solder thermal interface material having a higher thermal conductivity than the periphery seal, and a thermally conductive member attached to the periphery seal and the solder thermal interface material on a side thereof opposing the microelectronic die.

摘要翻译： 提供了一种微电子组件，其包括至少第一微电子管芯，其携带微电子电路，至少第一周边密封件附接到微电子管芯的表面的边缘，至少第一焊料热界面材料附着到中心区域 微电子管芯的表面，焊料热界面材料具有比周边密封件更高的热导率;以及导热构件，其附接到与微电子管芯相对的一侧上的外围密封件和焊料热界面材料。

公开(公告)号：US07633142B2

公开(公告)日：2009-12-15

申请号：US11977980

申请日：2007-10-26

申请人： Mitul B. Modi ,  Patricia A. Brusso ,  Ruben Cadena ,  Carolyn R. McCormick ,  Sankara J. Subramanian

发明人： Mitul B. Modi ,  Patricia A. Brusso ,  Ruben Cadena ,  Carolyn R. McCormick ,  Sankara J. Subramanian

IPC分类号： H01L23/12 ,  H05K7/00

CPC分类号： H01L23/145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/068 ,  H01L2924/00 ,  H01L2224/0401

摘要： An IC package is disclosed that comprises a core region disposed between upper and lower build-up layer regions. In one embodiment, the core region comprises a low modulus material. In an alternative embodiment the core region comprises a medium modulus material. In an alternative embodiment, the core material is selected based upon considerations such as it modulus, its coefficient of thermal expansion, and/or the resulting total accumulated strain. In an alternative embodiment, boundaries with respect to the softness of the core material are established be considering the reflective density in opposing conductive build-up layers above and below the core region.

摘要翻译： 公开了一种IC封装，其包括设置在上部和下部积聚层区域之间的芯区域。 在一个实施例中，芯区域包括低模量材料。 在替代实施例中，芯区域包括中等模量材料。 在替代实施例中，基于诸如其模量，其热膨胀系数和/或所得到的总累积应变的考虑来选择芯材料。 在替代实施例中，考虑到核心区域上方和下方的相对的导电堆积层中的反射密度，建立了关于芯材料的柔软度的边界。

公开(公告)号：US07352061B2

公开(公告)日：2008-04-01

申请号：US11134784

申请日：2005-05-20

申请人： Mitul B. Modi ,  Patricia A. Brusso ,  Ruben Cadena ,  Carolyn R. McCormick ,  Sankara J. Subramanian

发明人： Mitul B. Modi ,  Patricia A. Brusso ,  Ruben Cadena ,  Carolyn R. McCormick ,  Sankara J. Subramanian

IPC分类号： H01L23/12 ,  H05K7/00

CPC分类号： H01L23/145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/068 ,  H01L2924/00 ,  H01L2224/0401

摘要： An IC package is disclosed that comprises a core region disposed between upper and lower build-up layer regions. In one embodiment, the core region comprises a low modulus material. In an alternative embodiment the core region comprises a medium modulus material. In an alternative embodiment, the core material is selected based upon considerations such as its modulus, its coefficient of thermal expansion, and/or the resulting total accumulated strain. In an alternative embodiment, boundaries with respect to the softness of the core material are established by considering the relative density in opposing conductive build-up layers above and below the core region.

摘要翻译： 公开了一种IC封装，其包括设置在上部和下部积聚层区域之间的芯区域。 在一个实施例中，芯区域包括低模量材料。 在替代实施例中，芯区域包括中等模量材料。 在替代实施例中，基于诸如其模量，其热膨胀系数和/或所得到的总累积应变的考虑来选择芯材料。 在替代实施例中，通过考虑在芯区域上方和下方的相对的导电堆积层中的相对密度来建立关于芯材料的柔软度的边界。

公开(公告)号：US20130208411A1

公开(公告)日：2013-08-15

申请号：US13846218

申请日：2013-03-18

申请人： Patricia A. Brusso ,  Mitul B. Modi ,  Carolyn R. McCormick ,  Ruben Cadena ,  Sankara J. Subramanian ,  Edward L. Martin

发明人： Patricia A. Brusso ,  Mitul B. Modi ,  Carolyn R. McCormick ,  Ruben Cadena ,  Sankara J. Subramanian ,  Edward L. Martin

IPC分类号： H05K1/11 ,  G06F1/16

CPC分类号： H05K1/115 ,  G06F1/16 ,  H01L24/81 ,  H01L24/90 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/90 ,  H01L2924/14 ,  H01L2924/3511 ,  H05K3/305 ,  H05K3/3436 ,  H05K2201/10378 ,  H05K2203/1105 ,  Y02P70/613 ,  H01L2924/00

摘要： An underfill device and method have been are provided. Advantages of devices and methods shown include dissipation of stresses at an interface between components such as a chip package and an adjacent circuit board. Another advantage includes faster manufacturing time and ease of manufacture using underfill devices and methods shown. An underfill assembly can be pre made with conductive structures included within the underfill assembly. Steps such as flowing epoxy and curing can be eliminated or performed concurrently with other manufacturing steps.

摘要翻译： 提供了底部填充装置和方法。 显示的装置和方法的优点包括在诸如芯片封装和相邻电路板的部件之间的界面处的应力耗散。 另一个优势包括加快制造时间和使用底部填充装置的制造方便以及所示的方法。 底部填充组件可以预先制成包含在底部填充组件内的导电结构。 步骤如流动的环氧树脂和固化可以消除或与其他制造步骤同时进行。

公开(公告)号：US07692307B2

公开(公告)日：2010-04-06

申请号：US11636250

申请日：2006-12-08

申请人： Sudarshan Rangaraj ,  Shankar Ganapathysubramanian ,  Richard Harries ,  Mitul Modi ,  Sankara J. Subramanian

发明人： Sudarshan Rangaraj ,  Shankar Ganapathysubramanian ,  Richard Harries ,  Mitul Modi ,  Sankara J. Subramanian

IPC分类号： H01L23/48

CPC分类号： H05K1/0271 ,  H01L23/13 ,  H01L2924/0002 ,  H05K3/3436 ,  H05K2201/0133 ,  H05K2201/0187 ,  H05K2201/068 ,  Y10T29/49158 ,  H01L2924/00

摘要： A compliant structure for an electronic device comprises a substrate (110) composed of a first material (111) and a compliant zone (120) within the substrate. A plurality of solder joints (280) are located between, and form a connection between, the substrate and the electronic device (290). The compliant zone reduces the degree of deformation experienced by the solder joints due to thermal mismatch loading between the substrate and the die during attachment of the die to the substrate (chip attach). This reduction in solder joint deformation reduces the likelihood that the solder joints will crack.

摘要翻译： 用于电子设备的柔性结构包括由衬底内的第一材料（111）和柔性区（120）组成的衬底（110）。 多个焊接接头（280）位于衬底和电子器件（290）之间，并形成衬底和电子器件（290）之间的连接。 柔性区域在将管芯附着到衬底（芯片连接）期间由于衬底和裸片之间的热失配加载而减小焊点所经历的变形程度。 焊点变形的这种减少降低了焊点会破裂的可能性。

公开(公告)号：US08399291B2

公开(公告)日：2013-03-19

申请号：US11169518

申请日：2005-06-29

申请人： Patricia A Brusso ,  Mitul B Modi ,  Carolyn R. McCormick ,  Ruben Cadena ,  Sankara J Subramanian ,  Edward L. Martin

发明人： Patricia A Brusso ,  Mitul B Modi ,  Carolyn R. McCormick ,  Ruben Cadena ,  Sankara J Subramanian ,  Edward L. Martin

IPC分类号： H01L21/00

CPC分类号： H05K1/115 ,  G06F1/16 ,  H01L24/81 ,  H01L24/90 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/90 ,  H01L2924/14 ,  H01L2924/3511 ,  H05K3/305 ,  H05K3/3436 ,  H05K2201/10378 ,  H05K2203/1105 ,  Y02P70/613 ,  H01L2924/00

摘要： An underfill device and method have been are provided. Advantages of devices and methods shown include dissipation of stresses at an interface between components such as a chip package and an adjacent circuit board. Another advantage includes faster manufacturing time and ease of manufacture using underfill devices and methods shown. An underfill assembly can be pre made with conductive structures included within the underfill assembly. Steps such as flowing epoxy and curing can be eliminated or performed concurrently with other manufacturing steps.

摘要翻译： 提供了底部填充装置和方法。 显示的装置和方法的优点包括在诸如芯片封装和相邻电路板的部件之间的界面处的应力耗散。 另一个优势包括加快制造时间和使用底部填充装置的制造方便以及所示的方法。 底部填充组件可以预先制成包含在底部填充组件内的导电结构。 步骤如流动的环氧树脂和固化可以消除或与其他制造步骤同时进行。

公开(公告)号：US07719109B2

公开(公告)日：2010-05-18

申请号：US11541233

申请日：2006-09-29

申请人： Mitul Modi ,  Sudarshan V. Rangaraj ,  Shankar Ganapathysubramanian ,  Richard J. Harries ,  Sankara J. Subramanian

发明人： Mitul Modi ,  Sudarshan V. Rangaraj ,  Shankar Ganapathysubramanian ,  Richard J. Harries ,  Sankara J. Subramanian

IPC分类号： H01L23/10 ,  H01L23/34

CPC分类号： H01L23/147 ,  H01L23/15 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/162 ,  H05K3/4644 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/068 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A linear coefficient of thermal expansion (CTE) mismatch between two materials, such as between a microelectronic die and a mounting substrate, may induce stress at the interface of the materials. The temperature changes present during the process of attaching a die to a mounting substrate can cause cracking and failure in the electrical connections used to connect the die and mounting substrate. A material with a CTE approximately matching the die CTE is introduced in the mounting substrate to reduce the stress and cracking at the electrical connections between the die and mounting substrate. Additionally, this material may comprise thin film capacitors useful for decoupling power supplies.

摘要翻译： 两种材料（例如微电子管芯和安装衬底之间）的线性热膨胀系数（CTE）失配可能在材料的界面处引起应力。 在将管芯附接到安装基板的过程中存在的温度变化可能导致用于连接管芯和安装基板的电连接中的开裂和故障。 在安装基板中引入具有与模具CTE近似匹配的CTE的材料，以减少管芯和安装基板之间的电连接处的应力和开裂。 此外，该材料可以包括用于去耦电源的薄膜电容器。