公开(公告)号：US08575682B2

公开(公告)日：2013-11-05

申请号：US13323452

申请日：2011-12-12

Applicant: Bio Kim ,  Kihyun Hwang ,  Jaeyoung Ahn ,  SeungHyun Lim ,  Dongwoo Kim

Inventor： Bio Kim ,  Kihyun Hwang ,  Jaeyoung Ahn ,  SeungHyun Lim ,  Dongwoo Kim

IPC: H01L29/66

CPC classification number: H01L29/66666 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

Abstract: Provided are three-dimensional semiconductor memory devices and methods of forming the same. The device includes a substrate, conductive patterns stacked on the substrate, and an active pattern penetrating the conductive patterns to be connected to the substrate. The active pattern may include a first doped region provided in an upper portion of the active pattern, and a diffusion-resistant doped region overlapped with at least a portion of the first doped region. The diffusion-resistant doped region may be a region doped with carbon.

Abstract translation: 提供三维半导体存储器件及其形成方法。 该器件包括衬底，堆叠在衬底上的导电图案，以及穿透要连接到衬底的导电图案的有源图案。 有源图案可以包括设置在有源图案的上部的第一掺杂区域和与第一掺杂区域的至少一部分重叠的扩散阻抗掺杂区域。 扩散阻止掺杂区域可以是掺杂有碳的区域。

公开(公告)号：US20120153372A1

公开(公告)日：2012-06-21

申请号：US13323452

申请日：2011-12-12

Applicant: Bio Kim ,  Kihyun Hwang ,  Jaeyoung Ahn ,  SeungHyun Lim ,  Dongwoo Kim

Inventor： Bio Kim ,  Kihyun Hwang ,  Jaeyoung Ahn ,  SeungHyun Lim ,  Dongwoo Kim

IPC: H01L29/78

CPC classification number: H01L29/66666 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

Abstract: Provided are three-dimensional semiconductor memory devices and methods of forming the same. The device includes a substrate, conductive patterns stacked on the substrate, and an active pattern penetrating the conductive patterns to be connected to the substrate. The active pattern may include a first doped region provided in an upper portion of the active pattern, and a diffusion-resistant doped region overlapped with at least a portion of the first doped region. The diffusion-resistant doped region may be a region doped with carbon.

Abstract translation: 提供三维半导体存储器件及其形成方法。 该器件包括衬底，堆叠在衬底上的导电图案，以及穿透要连接到衬底的导电图案的有源图案。 有源图案可以包括设置在有源图案的上部的第一掺杂区域和与第一掺杂区域的至少一部分重叠的扩散阻抗掺杂区域。 扩散阻止掺杂区域可以是掺杂有碳的区域。

公开(公告)号：US10559584B2

公开(公告)日：2020-02-11

申请号：US15426797

申请日：2017-02-07

Applicant: Eun Yeoung Choi ,  Bio Kim ,  Young Wan Kim ,  Jung Ho Kim ,  Young Seon Son ,  Jae Young Ahn ,  Byong Hyun Jang

Inventor： Eun Yeoung Choi ,  Bio Kim ,  Young Wan Kim ,  Jung Ho Kim ,  Young Seon Son ,  Jae Young Ahn ,  Byong Hyun Jang

IPC: H01L27/11582 ,  H01L21/28 ,  H01L29/423

Abstract: A semiconductor device including a dielectric layer is provided. The semiconductor device includes a stack structure, and a vertical structure within the stack structure. The vertical structure includes a lower region having a first width and an upper region having a second width, greater than the first width. The vertical structure further includes two dielectric layers of which respective ratios of lower thicknesses in the lower region to upper thicknesses in the upper region are different from each other.

公开(公告)号：US09882018B2

公开(公告)日：2018-01-30

申请号：US14713039

申请日：2015-05-15

Applicant: Young Jin Noh ,  Jae Ho Choi ,  Bio Kim ,  Kwang Min Park ,  Jae Young Ahn ,  Dong Chul Yoo ,  Seung Hyun Lim ,  Jeon Il Lee

Inventor： Young Jin Noh ,  Jae Ho Choi ,  Bio Kim ,  Kwang Min Park ,  Jae Young Ahn ,  Dong Chul Yoo ,  Seung Hyun Lim ,  Jeon Il Lee

IPC: H01L29/51 ,  H01L29/792 ,  H01L29/788 ,  H01L27/11582 ,  H01L29/423 ,  H01L27/11556

CPC classification number: H01L29/518 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/7883 ,  H01L29/792

Abstract: A semiconductor device includes: a substrate including a channel region; a gate dielectric a tunneling layer, a charge storage layer, and a blocking layer sequentially disposed on the channel region; and a gate electrode disposed on the gate dielectric, wherein the tunneling layer has variations in nitrogen concentrations in a direction perpendicular to the channel region, and has a maximum nitrogen concentration in a position shifted from a center of the tunneling layer toward the charge storage layer.

公开(公告)号：US20180012902A1

公开(公告)日：2018-01-11

申请号：US15426797

申请日：2017-02-07

Applicant: Eun Yeoung Choi ,  Bio Kim ,  Young Wan Kim ,  Jung Ho Kim ,  Young Seon Son ,  Jae Young Ahn ,  Byong Hyun Jang

Inventor： Eun Yeoung Choi ,  Bio Kim ,  Young Wan Kim ,  Jung Ho Kim ,  Young Seon Son ,  Jae Young Ahn ,  Byong Hyun Jang

IPC: H01L29/423 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/42368

Abstract: A semiconductor device including a dielectric layer is provided. The semiconductor device includes a stack structure, and a vertical structure within the stack structure. The vertical structure includes a lower region having a first width and an upper region having a second width, greater than the first width. The vertical structure further includes two dielectric layers of which respective ratios of lower thicknesses in the lower region to upper thicknesses in the upper region are different from each other.

公开(公告)号：US09799657B2

公开(公告)日：2017-10-24

申请号：US15302032

申请日：2014-06-23

Applicant: Jintae Noh ,  Bio Kim ,  Su-Jin Shin ,  Hanvit Yang ,  Kihyun Hwang

Inventor： Jintae Noh ,  Bio Kim ,  Su-Jin Shin ,  Hanvit Yang ,  Kihyun Hwang

IPC: H01L21/033 ,  H01L27/105 ,  H01L21/02 ,  H01L21/311 ,  H01L29/40

CPC classification number: H01L27/1052 ,  H01L21/02323 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/32105 ,  H01L27/11582 ,  H01L29/401 ,  H01L29/7926

Abstract: The inventive concepts provide methods of manufacturing a semiconductor device. The method includes forming a thin layer structure including insulating layers and sacrificial layers alternately and repeatedly stacked on a substrate, forming a through-hole penetrating the thin layer structure and exposing the substrate, forming a semiconductor layer covering an inner sidewall of the through-hole and partially filling the through-hole, oxidizing a first portion of the semiconductor layer to form a first insulating layer, and injecting oxygen atoms into a second portion of the semiconductor layer. An oxygen atomic concentration of the second portion is lower than that of the first insulating layer. Oxidizing the first portion and injecting the oxygen atoms into the second portion are performed using an oxidation process at the same time.

公开(公告)号：US09515086B2

公开(公告)日：2016-12-06

申请号：US14834454

申请日：2015-08-25

Applicant: Gukhyon Yon ,  Jaeyoung Ahn ,  Bio Kim ,  Young-Jin Noh ,  Kwangmin Park ,  Dongchul Yoo

Inventor： Gukhyon Yon ,  Jaeyoung Ahn ,  Bio Kim ,  Young-Jin Noh ,  Kwangmin Park ,  Dongchul Yoo

IPC: H01L27/115 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L29/792

CPC classification number: H01L27/11582 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11556 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7926

Abstract: Provided are a three dimensional semiconductor memory device and a method of fabricating the same. In the three dimensional semiconductor memory device, a stack of gate electrodes and insulating layers may be formed on a substrate, a channel structure may extend through the stack and connect to the substrate. A blocking insulating layer, a charge storing layer and a tunnel insulating layer may be formed between each gate electrode and the channel structure. The tunnel insulating layer may include a high-k dielectric layer with a low charge trap site density. The tunnel insulating layer may also include a first and a second tunnel insulating layers, and the high-k dielectric layer is provided between the first and second tunnel insulating layers.

Abstract translation: 提供三维半导体存储器件及其制造方法。 在三维半导体存储器件中，可以在衬底上形成一叠栅极电极和绝缘层，沟道结构可以延伸通过堆叠并连接至衬底。 可以在每个栅电极和沟道结构之间形成阻挡绝缘层，电荷存储层和隧道绝缘层。 隧道绝缘层可以包括具有低电荷陷阱位点密度的高k电介质层。 隧道绝缘层还可以包括第一和第二隧道绝缘层，并且高k电介质层设置在第一和第二隧道绝缘层之间。

公开(公告)号：US20160118398A1

公开(公告)日：2016-04-28

申请号：US14834454

申请日：2015-08-25

Applicant: Gukhyon YON ,  Jaeyoung AHN ,  Bio KIM ,  Young-Jin NOH ,  Kwangmin PARK ,  Dongchul YOO

Inventor： Gukhyon YON ,  Jaeyoung AHN ,  Bio KIM ,  Young-Jin NOH ,  Kwangmin PARK ,  Dongchul YOO

IPC: H01L27/115 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L29/788

CPC classification number: H01L27/11582 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11556 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7926

Abstract: Provided are a three dimensional semiconductor memory device and a method of fabricating the same. In the three dimensional semiconductor memory device, a stack of gate electrodes and insulating layers may be formed on a substrate, a channel structure may extend through the stack and connect to the substrate. A blocking insulating layer, a charge storing layer and a tunnel insulating layer may be formed between each gate electrode and the channel structure. The tunnel insulating layer may include a high-k dielectric layer with a low charge trap site density. The tunnel insulating layer may also include a first and a second tunnel insulating layers, and the high-k dielectric layer is provided between the first and second tunnel insulating layers.

Abstract translation: 提供三维半导体存储器件及其制造方法。 在三维半导体存储器件中，可以在衬底上形成一叠栅极电极和绝缘层，沟道结构可以延伸通过堆叠并连接至衬底。 可以在每个栅电极和沟道结构之间形成阻挡绝缘层，电荷存储层和隧道绝缘层。 隧道绝缘层可以包括具有低电荷陷阱位点密度的高k电介质层。 隧道绝缘层还可以包括第一和第二隧道绝缘层，并且高k电介质层设置在第一和第二隧道绝缘层之间。

公开(公告)号：US10276589B2

公开(公告)日：2019-04-30

申请号：US15499291

申请日：2017-04-27

Applicant: Hyung Joon Kim ,  Yong Seok Cho ,  BiO Kim ,  Jung Ho Kim ,  Joong Yun Ra ,  Sung Hae Lee

Inventor： Hyung Joon Kim ,  Yong Seok Cho ,  BiO Kim ,  Jung Ho Kim ,  Joong Yun Ra ,  Sung Hae Lee

IPC: H01L27/11582 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L29/51 ,  H01L27/11565

Abstract: A method of manufacturing a semiconductor device includes forming a mold structure including alternately stacked mold insulating and sacrificial layers on a substrate, forming a vertical structure through the mold structure, forming side openings by removing the sacrificial, forming a preliminary dielectric layer in the side openings, forming a dielectric layer by heat-treating the preliminary dielectric layer, removing a surface layer of the dielectric layer, forming a first conductive layer covering the dielectric layer in the side openings, and forming a second conductive layer covering the first conductive layer and filling the side openings.

公开(公告)号：US20170162578A1

公开(公告)日：2017-06-08

申请号：US15302032

申请日：2014-06-23

Applicant: Jintae NOH ,  Bio KIM ,  Su-Jin SHIN ,  Hanvit YANG ,  Kihyun HWANG

Inventor： Jintae NOH ,  Bio KIM ,  Su-Jin SHIN ,  Hanvit YANG ,  Kihyun HWANG

IPC: H01L27/105 ,  H01L29/40 ,  H01L21/311 ,  H01L21/02 ,  H01L21/033

CPC classification number: H01L27/1052 ,  H01L21/02323 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/32105 ,  H01L27/11582 ,  H01L29/401 ,  H01L29/7926

Abstract: The inventive concepts provide methods of manufacturing a semiconductor device. The method includes forming a thin layer structure including insulating layers and sacrificial layers alternately and repeatedly stacked on a substrate, forming a through-hole penetrating the thin layer structure and exposing the substrate, forming a semiconductor layer covering an inner sidewall of the through-hole and partially filling the through-hole, oxidizing a first portion of the semiconductor layer to form a first insulating layer, and injecting oxygen atoms into a second portion of the semiconductor layer. An oxygen atomic concentration of the second portion is lower than that of the first insulating layer. Oxidizing the first portion and injecting the oxygen atoms into the second portion are performed using an oxidation process at the same time.