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14 条记录 (耗时 0.016 秒)

    INTERNAL VOLTAGE GENERATION CIRCUIT AND METHOD
    2.
    发明申请
    INTERNAL VOLTAGE GENERATION CIRCUIT AND METHOD 审中-公开
    内部电压发生电路及方法

    公开(公告)号：US20130093490A1

    公开(公告)日：2013-04-18

    申请号：US13333043

    申请日：2011-12-21

    申请人： Hyun Seok KIM ,  Ic Su OH ,  Jun Ho LEE ,  Boo Ho JUNG ,  Sun Ki CHO ,  Yang Hee KIM

    发明人： Hyun Seok KIM ,  Ic Su OH ,  Jun Ho LEE ,  Boo Ho JUNG ,  Sun Ki CHO ,  Yang Hee KIM

    IPC分类号： H03L5/00

    CPC分类号： H02M3/07 ,  H02M3/1584

    摘要： An internal voltage generation method includes the steps of: setting first to third sections by using a reference voltage; determining to which section an internal voltage level corresponds, among the first to third sections; and generating the internal voltage by controlling a voltage pumping amount according to a section corresponding to the internal voltage level.

    摘要翻译： 内部电压产生方法包括以下步骤：通过使用参考电压来设置第一至第三部分; 在第一至第三部分中确定内部电压电平对应于哪个部分; 以及通过根据对应于内部电压电平的部分控制电压抽取量来产生内部电压。

    Semiconductor integrated circuit
    4.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US08421528B2

    公开(公告)日：2013-04-16

    申请号：US13097326

    申请日：2011-04-29

    申请人： Hyun Seok Kim ,  Jun Ho Lee ,  Boo Ho Jung ,  Sun Ki Cho ,  Yang Hee Kim ,  Young Won Kim

    发明人： Hyun Seok Kim ,  Jun Ho Lee ,  Boo Ho Jung ,  Sun Ki Cho ,  Yang Hee Kim ,  Young Won Kim

    IPC分类号： G05F1/10

    CPC分类号： H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor integrated circuit includes a first voltage line to which a first ground voltage is applied, a second voltage line to which a second ground voltage is applied, a third voltage line to which a first power supply voltage is applied, and a coupling unit including a MOS transistor having a source coupled to the first voltage line, a drain coupled to the second voltage line, and a gate coupled to the third voltage line.

    摘要翻译： 半导体集成电路包括施加第一接地电压的第一电压线，施加第二接地电压的第二电压线，施加第一电源电压的第三电压线，以及包括 MOS晶体管，其具有耦合到第一电压线的源极，耦合到第二电压线的漏极和耦合到第三电压线的栅极。

    Semiconductor memory apparatus with power-meshed structure
    9.
    发明授权
    Semiconductor memory apparatus with power-meshed structure 失效
    具有电力网格结构的半导体存储器件

    公开(公告)号：US08503212B2

    公开(公告)日：2013-08-06

    申请号：US12843647

    申请日：2010-07-26

    申请人： Boo Ho Jung ,  Jun Ho Lee ,  Hyun Seok Kim ,  Sun Ki Cho ,  Yang Hee Kim ,  Young Won Kim

    发明人： Boo Ho Jung ,  Jun Ho Lee ,  Hyun Seok Kim ,  Sun Ki Cho ,  Yang Hee Kim ,  Young Won Kim

    IPC分类号： G11C5/06 ,  H01L23/52

    CPC分类号： G11C5/063 ,  G11C5/025

    摘要： A semiconductor memory apparatus includes a plurality of banks each having a plurality of cell mats; a plurality of power lines disposed over predetermined portions of each of the plurality of banks; a column control region disposed adjacent to at least one of sides of each bank which are perpendicular to an extending direction of the power lines; and a conductive plate disposed over the column control region and electrically connected to the plurality of power lines.

    摘要翻译： 一种半导体存储装置，包括：多个存储体，每个存储体具有多个单元格层; 多个电源线，布置在所述多个银行的每一个的预定部分上; 与每个组的至少一个侧面相邻设置的列控制区，其垂直于电力线的延伸方向; 以及设置在所述列控制区域上并电连接到所述多个电力线的导电板。

    SEMICONDUCTOR MEMORY APPARATUS WITH POWER-MESHED STRUCTURE
    10.
    发明申请
    SEMICONDUCTOR MEMORY APPARATUS WITH POWER-MESHED STRUCTURE 失效
    具有功率结构的半导体存储器件

    公开(公告)号：US20110235385A1

    公开(公告)日：2011-09-29

    申请号：US12843647

    申请日：2010-07-26

    申请人： Boo Ho JUNG ,  Jun Ho Lee ,  Hyun Seok Kim ,  Sun Ki Cho ,  Yang Hee Kim ,  Young Won Kim

    发明人： Boo Ho JUNG ,  Jun Ho Lee ,  Hyun Seok Kim ,  Sun Ki Cho ,  Yang Hee Kim ,  Young Won Kim

    IPC分类号： G11C5/02

    CPC分类号： G11C5/063 ,  G11C5/025

    摘要： A semiconductor memory apparatus includes a plurality of banks each having a plurality of cell mats; a plurality of power lines disposed over predetermined portions of each of the plurality of banks; a column control region disposed adjacent to at least one of sides of each bank which are perpendicular to an extending direction of the power lines; and a conductive plate disposed over the column control region and electrically connected to the plurality of power lines.

    摘要翻译： 一种半导体存储装置，包括：多个存储体，每个存储体具有多个单元格层; 多个电源线，布置在所述多个银行的每一个的预定部分上; 与每个组的至少一个侧面相邻设置的列控制区，其垂直于电力线的延伸方向; 以及设置在所述列控制区域上并电连接到所述多个电力线的导电板。