-
公开(公告)号：US07029977B2
公开(公告)日：2006-04-18
申请号：US10792884
申请日：2004-03-05
IPC分类号： H01L21/336 , H01L21/4763
CPC分类号： H01L29/0634 , C30B25/18 , C30B29/06 , H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L21/02639 , H01L21/3065 , H01L29/045 , H01L29/0688
摘要： A fabrication method of a semiconductor wafer can fill trenches formed in a semiconductor substrate with an epitaxial film with high crystal quality without leaving cavities in the trenches. The trenches are formed in the first conductivity type semiconductor substrate. Planes exposed inside the trenches are made clean surfaces by placing the substrate in a gas furnace, followed by supplying the furnace with an etching gas and carrier gas, and by performing etching on the exposed planes inside the trenches by a thickness from about a few nanometers to one micrometer. The trenches have a geometry opening upward through the etching. Following the etching, a second conductivity type semiconductor is epitaxially grown in the trenches by supplying the furnace with a growth gas, etching gas, doping gas and carrier gas, thereby filling the trenches. Instead of making the trenches slightly-opened upward, their sidewalls may be made planes enabling facet formation.
摘要翻译： 半导体晶片的制造方法可以用具有高晶体质量的外延膜填充在半导体衬底中形成的沟槽，而不会在沟槽中留下空洞。 沟槽形成在第一导电型半导体衬底中。 通过将衬底放置在气体炉中，然后向炉内供应蚀刻气体和载气，并且通过在沟槽内的暴露平面上蚀刻约几纳米的厚度，将暴露在沟槽内的平面制成干净的表面 至一微米。 沟槽具有通过蚀刻向上的几何形状。 在蚀刻之后，通过向炉提供生长气体，蚀刻气体，掺杂气体和载气，从而在沟槽中外延生长第二导电型半导体，由此填充沟槽。 不是使沟槽向上略微打开，它们的侧壁可以制成使得能够形成小平面的平面。
-
公开(公告)号：US07355257B2
公开(公告)日：2008-04-08
申请号：US11370188
申请日：2006-03-08
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/157 , H01L29/7813 , H01L29/7825 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor superjunction device has a superjunction structure formed in a drift region of the device. The superjunction structure has alternately arranged n-type regions and p-type semiconductor regions layered parallel with the drift direction of carriers, permitting current flow when turned ON and depleting when turned OFF. It also includes a first intrinsic semiconductor region between the n-type and p-type regions. The first intrinsic semiconductor region and the n-type and p-type regions sandwiching the first intrinsic semiconductor region forming a unit. A plurality of units are repetitively arranged to form a repetitively arranged structure. The value of mobility of one of electrons in the n-type region or holes in the p-type region is equal to or less than half the value of mobility of corresponding to one of electrons or holes in the first intrinsic semiconductor region. The superjunction structure eliminates the lower limit that prevents further narrowing of the widths of the n-type and p-type regions to further improve the tradeoff relationship between increasing the breakdown voltage and reducing the on-resistance.
摘要翻译： 半导体超结装置具有形成在装置的漂移区域中的超结构结构。 超结构结构交替布置与载流子漂移方向平行分布的n型区域和p型半导体区域，当导通时允许电流流动并且在关断时耗尽。 它还包括n型和p型区之间的第一本征半导体区。 第一本征半导体区域和夹着形成单元的第一本征半导体区域的n型和p型区域。 重复地布置多个单元以形成重复排列的结构。 n型区域中的电子之一或p型区域中的空穴的迁移率的值等于或小于对应于第一本征半导体区域中的电子或空穴之一的迁移率的值的一半。 超结结构消除了阻止n型和p型区域的宽度进一步变窄的下限，以进一步提高增加击穿电压和降低导通电阻之间的折衷关系。
-
公开(公告)号：US20060256487A1
公开(公告)日：2006-11-16
申请号：US11370188
申请日：2006-03-08
IPC分类号： H02H7/00
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/157 , H01L29/7813 , H01L29/7825 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor superjunction device has a superjunction structure formed in a drift region of the device. The superjunction structure has alternately arranged n-type regions and p-type semiconductor regions layered parallel with the drift direction of carriers, permitting current flow when turned ON and depleting when turned OFF. It also includes a first intrinsic semiconductor region between the n-type and p-type regions. The first intrinsic semiconductor region and the n-type and p-type regions sandwiching the first intrinsic semiconductor region forming a unit. A plurality of units are repetitively arranged to form a repetitively arranged structure. The value of mobility of one of electrons in the n-type region or holes in the p-type region is equal to or less than half the value of mobility of corresponding to one of electrons or holes in the first intrinsic semiconductor region. The superjunction structure eliminates the lower limit that prevents further narrowing of the widths of the n-type and p-type regions to further improve the tradeoff relationship between increasing the breakdown voltage and reducing the on-resistance.
摘要翻译： 半导体超结装置具有形成在装置的漂移区域中的超结构结构。 超结构结构交替布置与载流子漂移方向平行分布的n型区域和p型半导体区域，当导通时允许电流流动并且在关断时耗尽。 它还包括n型和p型区之间的第一本征半导体区。 第一本征半导体区域和夹着形成单元的第一本征半导体区域的n型和p型区域。 重复地布置多个单元以形成重复排列的结构。 n型区域中的电子之一或p型区域中的空穴的迁移率的值等于或小于对应于第一本征半导体区域中的电子或空穴之一的迁移率的值的一半。 超结结构消除了阻止n型和p型区域的宽度进一步变窄的下限，以进一步提高增加击穿电压和降低导通电阻之间的折衷关系。
-
公开(公告)号：US06674126B2
公开(公告)日：2004-01-06
申请号：US10073671
申请日：2002-02-11
申请人： Susumu Iwamoto , Tatsuhiko Fujihira , Katsunori Ueno , Yasuhiko Onishi , Takahiro Sato , Tatsuji Nagaoka
发明人： Susumu Iwamoto , Tatsuhiko Fujihira , Katsunori Ueno , Yasuhiko Onishi , Takahiro Sato , Tatsuji Nagaoka
IPC分类号： A01L29772
CPC分类号： H01L29/7802 , H01L29/0634
摘要： A semiconductor device facilitates obtaining a higher breakdown voltage in the portion of the semiconductor chip around the drain drift region and improving the avalanche withstanding capability thereof. A vertical MOSFET according to the invention includes a drain layer; a drain drift region on drain layer, drain drift region including a first alternating conductivity type layer; a breakdown withstanding region (the peripheral region of the semiconductor chip) on drain layer and around drain drift region, breakdown withstanding region providing substantially no current path in the ON-state of the MOSFET, breakdown withstanding region being depleted in the OFF-state of the MOSFET, breakdown withstanding region including a second alternating conductivity type layer, and an under region below a gate pad, and the under region including a third alternating conductivity type layer.
摘要翻译： 半导体器件有助于在漏极漂移区周围的半导体芯片的部分中获得更高的击穿电压并且提高其雪崩耐受能力。 根据本发明的垂直MOSFET包括漏极层; 漏极层上的漏极漂移区，包括第一交替导电型层的漏极漂移区; 在漏极层和漏极漂移区域周围的击穿耐受区域（半导体芯片的外围区域），在MOSFET的导通状态基本上不提供电流路径的击穿承受区域，击穿耐受区域在断开状态 MOSFET，包括第二交替导电类型层的击穿耐受区域和栅极焊盘下方的下部区域，以及包括第三交变导电类型层的下部区域。
-
5.发明授权公开(公告)号：US06291856B1
公开(公告)日：2001-09-18
申请号：US09438078
申请日：1999-11-10
IPC分类号： H01L2976
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/1095 , H01L29/7395
摘要： This invention clarifies the effects of parameters and enables the mass production of a super-junction semiconductor device, which has a drift layer composed of a parallel pn layer that conducts electricity in the ON state and is depleted in the OFF state. The quantity of impurities in n drift regions is within the range between 100% and 150% or between 110% and 150% of the quantity of impurities in p partition regions. The impurity density of either one of the n drift regions and the p partition regions is within the range between 92% and 108% of the impurity density of the other regions. In addition, the width of either one of the n drift regions and the p partition regions is within the range between 94% and 106% of the width of the other regions.
摘要翻译： 本发明澄清了参数的影响，并且能够批量生产具有在导通状态下导通电并且耗尽OFF状态的并联pn层构成的漂移层的超结半导体器件。 n个漂移区域中的杂质量在p分配区域中的杂质量的100％至150％之间或110％至150％的范围内。 n个漂移区域和p个分割区域中的任一个的杂质浓度在其他区域的杂质浓度的92％〜108％的范围内。 此外，n个漂移区域和p个分割区域中的任一个的宽度在其他区域的宽度的94％和106％之间的范围内。
-
公开(公告)号：US07042046B2
公开(公告)日：2006-05-09
申请号：US10925407
申请日：2004-08-25
申请人： Yasuhiko Onishi , Tatsuhiko Fujihira , Katsunori Ueno , Susumu Iwamoto , Takahiro Sato , Tatsuji Nagaoka
发明人： Yasuhiko Onishi , Tatsuhiko Fujihira , Katsunori Ueno , Susumu Iwamoto , Takahiro Sato , Tatsuji Nagaoka
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/0634 , H01L29/0696 , H01L29/66333 , H01L29/66712 , H01L29/7395 , H01L29/7802 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted. Thus, the breakdown voltage of breakdown withstanding region is higher than the breakdown voltage of drain drift region.
-
公开(公告)号：US07002205B2
公开(公告)日：2006-02-21
申请号：US10735501
申请日：2003-12-12
申请人： Yasuhiko Onishi , Tatsuhiko Fujihira , Katsunori Ueno , Susumu Iwamoto , Takahiro Sato , Tatsuji Nagaoka
发明人： Yasuhiko Onishi , Tatsuhiko Fujihira , Katsunori Ueno , Susumu Iwamoto , Takahiro Sato , Tatsuji Nagaoka
IPC分类号： H01L29/76
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/0634 , H01L29/0696 , H01L29/66333 , H01L29/66712 , H01L29/7395 , H01L29/7802 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted. Thus, the breakdown voltage of breakdown withstanding region is higher than the breakdown voltage of drain drift region.
摘要翻译： 公开了一种半导体器件，其使用其周边部分具有高于漏极漂移层中的击穿电压的击穿电压，而不采用保护环或场板。 优选实施例包括漏极漂移区，其具有由n个漂移电流通路区域和彼此交替布置的p个分隔区域形成的第一交变导电类型层，以及具有由n个区域和p形成的第二交变导电类型层的击穿承受区域 区域彼此交替布置，击穿承受区域在设备的接通状态下不提供电流路径，并且在器件的关断状态被耗尽。 由于耗尽层从多个pn结到两个方向扩展到设备的OFF状态的n个区域和p区域，所以p型基极区域的相邻区域，半导体芯片的外部区域和 半导体芯片耗尽。 因此，击穿耐受区域的击穿电压高于漏极漂移区域的击穿电压。
-
公开(公告)号：US06724042B2
公开(公告)日：2004-04-20
申请号：US09781066
申请日：2001-02-09
申请人： Yasuhiko Onishi , Tatsuhiko Fujihira , Katsunori Ueno , Susumu Iwamoto , Takahiro Sato , Tatsuji Nagaoka
发明人： Yasuhiko Onishi , Tatsuhiko Fujihira , Katsunori Ueno , Susumu Iwamoto , Takahiro Sato , Tatsuji Nagaoka
IPC分类号： H01L2976
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/0634 , H01L29/0696 , H01L29/66333 , H01L29/66712 , H01L29/7395 , H01L29/7802 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted. Thus, the breakdown voltage of breakdown withstanding region is higher than the breakdown voltage of drain drift region.
摘要翻译： 公开了一种半导体器件，其使用其周边部分具有高于漏极漂移层中的击穿电压的击穿电压，而不采用保护环或场板。 优选实施例包括漏极漂移区，其具有由n个漂移电流通路区域和彼此交替布置的p个分隔区域形成的第一交变导电类型层，以及具有由n个区域和p形成的第二交变导电类型层的击穿承受区域 区域彼此交替布置，击穿承受区域在设备的接通状态下不提供电流路径，并且在器件的关断状态被耗尽。 由于耗尽层从多个pn结到两个方向扩展到设备的OFF状态的n个区域和p区域，所以p型基极区域的相邻区域，半导体芯片的外部区域和 半导体芯片耗尽。 因此，击穿耐受区域的击穿电压高于漏极漂移区域的击穿电压。
-
公开(公告)号：US06700141B2
公开(公告)日：2004-03-02
申请号：US09978847
申请日：2001-10-17
IPC分类号： H01L2936
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/7802
摘要： A reliable super-junction semiconductor device is provided that facilitates relaxing the tradeoff relation between the on-resistance and the breakdown voltage and improving the avalanche withstanding capability under an inductive load. The super-junction semiconductor device includes an active region including a thin first alternating conductivity type layer and a heavily doped n+-type intermediate drain layer between first alternating conductivity type layer and an n++-type drain layer, and a breakdown withstanding region including a thick second alternating conductivity type layer. Alternatively, active region includes a first alternating conductivity type layer and a third alternating conductivity type layer between first alternating conductivity type layer and n++-type drain layer, third alternating conductivity type layer being doped more heavily than first alternating conductivity type layer.
摘要翻译： 提供了可靠的超结半导体器件，其有助于放松导通电阻和击穿电压之间的折衷关系，并提高在感性负载下的雪崩耐受能力。 超结半导体器件包括在第一交替导电型层和n ++类漏极层之间包括薄的第一交替导电型层和重掺杂n +型中间漏极层的有源区，以及 包括厚的第二交替导电类型层的击穿耐受区域。 或者，有源区包括第一交替导电类型层和第n +型漏极之间的第一交变导电类型层和第三交变导电类型层，第三交变导电类型层比第一交变导电类型层更重掺杂 。
-
公开(公告)号：US06677643B2
公开(公告)日：2004-01-13
申请号：US09811727
申请日：2001-03-19
IPC分类号： H01L2976
CPC分类号： H01L21/26513 , H01L21/266 , H01L29/0634 , H01L29/1095 , H01L29/7802
摘要： A super-junction semiconductor is provided that facilitates easy mass-production thereof, reducing the tradeoff relation between the on-resistance and the breakdown voltage, obtaining a high breakdown voltage and reducing the on-resistance to increase the current capacity thereof. The super-junction semiconductor device includes a semiconductor chip having a first major surface and a second major surface facing in opposite to the first major surface; a layer with low electrical resistance on the side of the second major surface; a first alternating conductivity type layer on low resistance layer, and a second alternating conductivity type layer on the first alternating conductivity type layer. The first alternating conductivity type layer including regions of a first conductivity type and regions of a second conductivity type arranged alternately with each other. The second alternating conductivity type layer including regions of the first conductivity type and regions of the second conductivity type arranged alternately with each other. The spacing between the pn-junctions in the second alternating conductivity type layer is wider than the spacing between the pn-junctions in the first alternating conductivity type layer.
摘要翻译： 提供了一种能够容易地进行批量生产，降低导通电阻和击穿电压之间的折衷关系的超结半导体，获得高的击穿电压并降低导通电阻以增加其电流容量。 超结半导体器件包括具有第一主表面和面向第一主表面的第二主表面的半导体芯片; 在第二主表面侧具有低电阻的层; 低电阻层上的第一交替导电类型层和第一交变导电类型层上的第二交变导电类型层。 第一交变导电类型层包括彼此交替排列的第一导电类型的区域和第二导电类型的区域。 包括第一导电类型的区域和第二导电类型的区域的第二交替导电类型层彼此交替排列。 第二交变导电类型层中的pn结之间的间隔比第一交变导电类型层中的pn结之间的间隔宽。
-
-
-
-
-
-
-
-
-
搜索结果
33 条记录 (耗时 0.022 秒)
