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    DIELECTRIC BODY AND METHOD FOR PRODUCTION THEREOF
    1.
    发明申请
    DIELECTRIC BODY AND METHOD FOR PRODUCTION THEREOF 有权
    介电体及其生产方法

    公开(公告)号：US20100271749A1

    公开(公告)日：2010-10-28

    申请号：US12570754

    申请日：2009-09-30

    申请人： Tae-Kyoung KIM ,  Ho-Gyu Yoon ,  Jin-Cheol Kim

    发明人： Tae-Kyoung KIM ,  Ho-Gyu Yoon ,  Jin-Cheol Kim

    IPC分类号： H01G4/00 ,  C04B35/00

    CPC分类号： C04B35/4682 ,  C04B2235/3213 ,  H01G4/1227 ,  H01G4/14 ,  H01G4/206 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K1/162 ,  H05K2201/0209 ,  H01L2924/00

    摘要： A dielectric body and a method of producing the dielectric body are disclosed. In accordance with an embodiment of the present invention, the dielectric body using a polymer matrix and being expressed in the following Reaction Scheme 1 includes two or more kinds of ceramic fillers having different x values in the following Reaction Scheme 1. In this way, a dielectric body having a stable dielectric constant as well as a high dielectric constant against the change in temperature can be manufactured. Ba1-xSrxTiO3  [Reaction Scheme 1] whereas 0≦x≦1.

    摘要翻译： 公开了介电体及其制造方法。 根据本发明的实施方案，使用聚合物基质并在下列反应流程图1中表示的电介质体包括在以下反应方案1中具有不同x值的两种或更多种陶瓷填料。以这种方式， 可以制造具有稳定介电常数以及抵抗温度变化的高介电常数的介电体。 Ba1-xSrxTiO3 [反应方案1]，而0＆nlE; x＆lt; 1;

    Printed circuit board using paste bump and manufacturing method thereof
    2.
    发明申请
    Printed circuit board using paste bump and manufacturing method thereof 有权
    使用糊状凸块的印刷电路板及其制造方法

    公开(公告)号：US20080283288A1

    公开(公告)日：2008-11-20

    申请号：US12219381

    申请日：2008-07-21

    申请人： Jee-Soo Mok ,  Chang-Sup Ryu ,  Eung-Suek Lee ,  Youn-Soo Seo ,  Hee-Bum Shin ,  Yoong Oh ,  Byung-Bae Seo ,  Tae-Kyoung Kim ,  Dong-Jin Park

    发明人： Jee-Soo Mok ,  Chang-Sup Ryu ,  Eung-Suek Lee ,  Youn-Soo Seo ,  Hee-Bum Shin ,  Yoong Oh ,  Byung-Bae Seo ,  Tae-Kyoung Kim ,  Dong-Jin Park

    IPC分类号： H05K1/11

    CPC分类号： H05K3/462 ,  H01R12/523 ,  H05K3/4069 ,  H05K3/4647 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/0353 ,  Y10T29/49155

    摘要： A printed circuit board using paste bumps and manufacturing method thereof are disclosed. The method of manufacturing a printed circuit board using paste bumps, includes: (a) perforating a core board to form at least one via hole, (b) filling the at least one via hole by fill-plating and forming a circuit pattern on at least one surface of the core board, (c) stacking a paste bump board on at least one surface of the core board, and (d) forming an outer layer circuit on a surface of the paste bump board, a structurally stable all-layer IVH structure can be implemented due to increased strength in the BVH's of the plated core boards, the manufacture time can be reduced due to parallel processes and collective stacking, implementing micro circuits can be made easy due to the copper foils of the paste bump boards stacked on the outermost layers, the manufacture costs can be reduced as certain plating and drilling processes may be omitted, the interlayer connection area is increased between circuit patterns for improved connection reliability, and dimple coverage can be obtained.

    摘要翻译： 公开了一种使用糊状凸块的印刷电路板及其制造方法。 使用糊状凸块制造印刷电路板的方法包括：（a）穿孔芯板以形成至少一个通孔，（b）通过填充电镀填充至少一个通孔并在其上形成电路图案 芯板的至少一个表面，（c）在芯板的至少一个表面上堆叠焊料凸块，以及（d）在焊料凸块的表面上形成外层电路，结构稳定的全层 由于镀层芯板的BVH的强度增加，可以实现IVH结构，由于并行处理和集体堆叠，制造时间可以减少，由于糊状凸块的铜箔堆叠而实现微电路变得容易 在最外层，可以减少制造成本，因为可以省略某些电镀和钻孔工艺，在电路图案之间增加层间连接面积以提高连接可靠性，并且可以获得凹坑覆盖 d。

    Capacitor embedded printed circuit board
    3.
    发明申请
    Capacitor embedded printed circuit board 有权
    电容器嵌入式印刷电路板

    公开(公告)号：US20080223603A1

    公开(公告)日：2008-09-18

    申请号：US12068790

    申请日：2008-02-12

    申请人： Jin Cheol Kim ,  Tae Kyoung Kim ,  Jun Rok Oh

    发明人： Jin Cheol Kim ,  Tae Kyoung Kim ,  Jun Rok Oh

    IPC分类号： H05K1/16

    CPC分类号： H05K1/162 ,  H05K3/4602 ,  H05K3/4652 ,  H05K3/4688 ,  H05K2201/09672 ,  H05K2203/061

    摘要： A capacitor embedded printed circuit board (PCB), the PCB including: a multilayer polymer capacitor layer where a plurality of polymer sheets is laminated; one or more first inner electrodes and second inner electrodes, separated by one or more of the plurality of polymer sheets and alternately disposed to form a pair; a plurality of first extended electrodes and second extended electrodes connected to the first inner electrodes and second inner electrodes, respectively; one or more insulating layers laminated on one or both surfaces of the multilayer polymer capacitor, where a plurality of conductive patterns and conductive via holes, forming an interlayer circuit are formed; a plurality of first via holes for capacitor, penetrating the multilayer polymer capacitor layer to be connected to the first extended electrodes; and a plurality of second via holes for capacitor, penetrating the multilayer polymer capacitor layer to be connected to the second extended electrodes, wherein the plurality of the first and second extended electrodes are alternately disposed to be opposite to each other.

    摘要翻译： 一种电容器嵌入式印刷电路板（PCB），所述PCB包括：层叠多个聚合物片的多层聚合物电容器层; 一个或多个第一内部电极和第二内部电极，由多个聚合物片中的一个或多个隔开并交替地设置成一对; 分别连接到第一内部电极和第二内部电极的多个第一延伸电极和第二延伸电极; 层叠在所述多层聚合物电容器的一面或两面上的一个以上的绝缘层，其中形成形成层间电路的多个导电图案和导电通孔; 多个用于电容器的第一通孔，穿过要连接到第一延伸电极的多层聚合物电容器层; 以及多个用于电容器的第二通孔，穿过要连接到第二延伸电极的多层聚合物电容器层，其中多个第一和第二延伸电极交替地设置成彼此相对。

    Method for monitoring an ion implanter and ion implanter having a shadow jig for performing the same
    6.
    发明授权
    Method for monitoring an ion implanter and ion implanter having a shadow jig for performing the same 失效
    用于监测离子注入机和离子注入机的方法，其具有用于执行该离子注入机的阴影夹具

    公开(公告)号：US06800863B2

    公开(公告)日：2004-10-05

    申请号：US10634756

    申请日：2003-08-06

    申请人： Chung-Sam Jun ,  Sun-Yong Choi ,  Dong-Chun Lee ,  Tae-kyoung Kim ,  Doo-Guen Song ,  Seung-Won Chae

    发明人： Chung-Sam Jun ,  Sun-Yong Choi ,  Dong-Chun Lee ,  Tae-kyoung Kim ,  Doo-Guen Song ,  Seung-Won Chae

    IPC分类号： H01J37317

    CPC分类号： H01J37/3045 ,  H01J37/3171

    摘要： A method for monitoring an ion implanter includes positioning a substrate behind an interceptor for intercepting a portion of an ion beam to be irradiated toward the substrate, irradiating a first ion beam toward the substrate to form a first shadow on the substrate, rotating the substrate about a central axis of the substrate, irradiating a second ion beam toward the substrate to form a second shadow on the substrate, and measuring a dosage of ions implanted into the substrate to monitor whether the rotation of the substrate has been normally performed. Preferably, a dosage of ions implanted into the substrate is calculated from a thermal wave value of the substrate and whether the rotation of the substrate has been normally performed is monitored by comparing the thermal wave value corresponding to the first shadow with a reference thermal wave value.

    摘要翻译： 一种用于监测离子注入机的方法包括将基片定位在拦截器后面，用于截取要朝向基板照射的离子束的一部分，向基板照射第一离子束，以在基板上形成第一阴影， 基板的中心轴，向基板照射第二离子束，在基板上形成第二阴影，并测量注入到基板中的离子的剂量，以监测基板的旋转是否正常进行。 优选地，通过将​​对应于第一阴影的热波值与参考热波值进行比较来监测从衬底的热波值和衬底的旋转是否正常地进行的植入衬底中的离子的剂量 。

    Method of recording holographic information using hologram mark and homogeneous mark
    7.
    发明授权
    Method of recording holographic information using hologram mark and homogeneous mark 失效
    使用全息标记和均匀标记记录全息信息的方法

    公开(公告)号：US08270051B2

    公开(公告)日：2012-09-18

    申请号：US12503192

    申请日：2009-07-15

    申请人： Taek-seong Jeong ,  Tae-kyoung Kim ,  Jae-cheol Bae

    发明人： Taek-seong Jeong ,  Tae-kyoung Kim ,  Jae-cheol Bae

    IPC分类号： G03H1/02

    CPC分类号： G11B7/0065 ,  G11B7/00772 ,  G11B7/083 ,  G11B2007/0009

    摘要： A method of recording holographic information includes recording a hologram mark and a homogeneous mark in a holographic data storage medium with a volume to alternatively locate the hologram mark and the homogeneous mark. The hologram mark has a varied refractive index distribution due to constructive/destructive interferences between two light beams and indicates information, while the homogeneous mark has a more uniform refractive index distribution than the hologram mark.

    摘要翻译： 记录全息信息的方法包括在具有体积的全息数据存储介质中记录全息标记和均匀标记，以交替地定位全息标记和均匀标记。 由于两个光束之间的建构性/破坏性干扰，全息图标记具有不同的折射率分布，并且指示信息，而均匀标记具有比全息标记更均匀的折射率分布。

    Printed circuit board using paste bump and manufacturing method thereof
    8.
    发明授权
    Printed circuit board using paste bump and manufacturing method thereof 有权
    使用糊状凸块的印刷电路板及其制造方法

    公开(公告)号：US07973248B2

    公开(公告)日：2011-07-05

    申请号：US12219381

    申请日：2008-07-21

    申请人： Jee-Soo Mok ,  Chang-Sup Ryu ,  Eung-Suek Lee ,  Youn-Soo Seo ,  Hee-Bum Shin ,  Yoong Oh ,  Byung-Bae Seo ,  Tae-Kyoung Kim ,  Dong-Jin Park

    发明人： Jee-Soo Mok ,  Chang-Sup Ryu ,  Eung-Suek Lee ,  Youn-Soo Seo ,  Hee-Bum Shin ,  Yoong Oh ,  Byung-Bae Seo ,  Tae-Kyoung Kim ,  Dong-Jin Park

    IPC分类号： H01R12/04 ,  H05K1/11

    CPC分类号： H05K3/462 ,  H01R12/523 ,  H05K3/4069 ,  H05K3/4647 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/0353 ,  Y10T29/49155

    摘要： A printed circuit board using paste bumps and manufacturing method thereof are disclosed. The method of manufacturing a printed circuit board using paste bumps, includes: (a) perforating a core board to form at least one via hole, (b) filling the at least one via hole by fill-plating and forming a circuit pattern on at least one surface of the core board, (c) stacking a paste bump board on at least one surface of the core board, and (d) forming an outer layer circuit on a surface of the paste bump board, a structurally stable all-layer IVH structure can be implemented due to increased strength in the BVH's of the plated core boards, the manufacture time can be reduced due to parallel processes and collective stacking, implementing micro circuits can be made easy due to the copper foils of the paste bump boards stacked on the outermost layers, the manufacture costs can be reduced as certain plating and drilling processes may be omitted, the interlayer connection area is increased between circuit patterns for improved connection reliability, and dimple coverage can be obtained.

    摘要翻译： 公开了一种使用糊状凸块的印刷电路板及其制造方法。 使用糊状凸块制造印刷电路板的方法包括：（a）穿孔芯板以形成至少一个通孔，（b）通过填充电镀填充至少一个通孔并在其上形成电路图案 芯板的至少一个表面，（c）在芯板的至少一个表面上堆叠焊料凸块，以及（d）在焊料凸块的表面上形成外层电路，结构稳定的全层 由于镀层芯板的BVH的强度增加，可以实现IVH结构，由于并行处理和集体堆叠，制造时间可以减少，由于粘贴凸块的铜箔堆叠而实现微电路变得容易 在最外层，可以减少制造成本，因为可以省略某些电镀和钻孔工艺，在电路图案之间增加层间连接面积以提高连接可靠性，并且可以获得凹坑覆盖 d。

    Wafer holder and wafer conveyor equipped with the same
    9.
    发明授权
    Wafer holder and wafer conveyor equipped with the same 失效
    晶圆架和晶圆输送机配备相同

    公开(公告)号：US07666069B2

    公开(公告)日：2010-02-23

    申请号：US11783534

    申请日：2007-04-10

    申请人： Tae-Kyoung Kim ,  Yun-Jung Jee ,  Kyoung-Su Shin ,  Chung-Sam Jun

    发明人： Tae-Kyoung Kim ,  Yun-Jung Jee ,  Kyoung-Su Shin ,  Chung-Sam Jun

    IPC分类号： B24B47/02

    CPC分类号： H01L21/68785 ,  H01L21/6776

    摘要： The present invention is directed to a wafer holder and a related wafer conveyor system. The wafer holder holds a wafer and moves horizontally within a chamber. A contact area between the wafer and the wafer holder is reduced, and potential contaminants generated by ear between components of the wafer holder are trapped by an airtight cover. Since the wafer holder moves horizontally while being fixed to a guide rail, the wafer conveyor system reduces friction between the guide rail and the wafer holder.

    摘要翻译： 本发明涉及晶片保持器和相关的晶片输送系统。 晶片保持器保持晶片并且在腔室内水平移动。 晶片和晶片保持架之间的接触面积减小，并且由晶片保持器的部件之间的耳朵产生的潜在的污染物被气密的盖子所困住。 由于晶片保持架在固定到导轨的同时水平移动，所以晶片传送系统减小了导轨和晶片保持器之间的摩擦。