公开(公告)号：US4807011A

公开(公告)日：1989-02-21

申请号：US24930

申请日：1987-03-10

Applicant: Terumoto Nonaka ,  Tadahiko Hotta

Inventor： Terumoto Nonaka ,  Tadahiko Hotta

IPC: H01L21/8222 ,  H01L27/06 ,  H01L27/098 ,  H01L29/772 ,  H01L29/80 ,  H01L29/68 ,  H01L27/04

CPC classification number: H01L29/7722 ,  H01L27/098 ,  H01L29/80

Abstract: A semiconductor integrated circuit comprising a plurality of vertical static induction transistors (SITs) of normally-off type formed in a common semiconductor substrate in such a manner that the lateral dimension of the channel region of the SITs employed to form a hardware circuit region such as a logic circuit is designed greater than of the SITs which are employed to form a peripheral circuit region. Thus, it is possible to provide a semiconductor integrated circuit which concurrently satisfies a plurality of differently functioning semiconductor circuit requirements to exhibit different electric characteristics as represented by a high-speed operation and a high breakdown voltage.

Abstract translation: 一种半导体集成电路，包括形成在公共半导体衬底中的多个垂直静态感应晶体管（SIT），其以常规半导体衬底的方式使得SIT的沟道区域的横向尺寸形成硬件电路区域 逻辑电路被设计为大于用于形成外围电路区域的SIT的逻辑电路。 因此，可以提供同时满足多个不同功能的半导体电路要求的半导体集成电路，以呈现由高速操作和高击穿电压表示的不同的电特性。

公开(公告)号：US4409725A

公开(公告)日：1983-10-18

申请号：US309428

申请日：1981-10-07

Applicant: Tadahiko Hotta ,  Terumoto Nonaka

Inventor： Tadahiko Hotta ,  Terumoto Nonaka

IPC: H01L21/8238 ,  H01L21/8249 ,  H01L27/085 ,  H01L21/22 ,  H01L21/306 ,  H01L29/76

CPC classification number: H01L21/8249 ,  H01L21/8238 ,  H01L27/085

Abstract: A method of making a semiconductor integrated circuit on a semiconductor substrate containing thereon an SIT and an IG(MOS) FET or an SIT and C-MOS FETs, comprises a series of steps of making these functional semiconductor devices many of which steps are rendered to be common to the SIT and the FET. The gate region of said IG(MOS) FET is formed as a semiconductor gate layer which typically is made of polycrystalline silicon, and an active semiconductor area of said IG(MOS) FET is formed by using this semiconductor gate layer as the mask therefor.

Abstract translation: 在其上包含SIT和IG（MOS）FET或SIT和C-MOS FET的半导体衬底上制造半导体集成电路的方法包括使这些功能半导体器件成为许多步骤的一系列步骤 对于SIT和FET是常见的。 所述IG（MOS）FET的栅极区域形成为通常由多晶硅制成的半导体栅极层，并且通过使用该半导体栅极层作为掩模来形成所述IG（MOS）FET的有源半导体区域。

公开(公告)号：US4234803A

公开(公告)日：1980-11-18

申请号：US899588

申请日：1978-04-24

Applicant: Terumoto Nonaka

Inventor： Terumoto Nonaka

IPC: H01L21/8222 ,  H01L21/33 ,  H01L21/8248 ,  H01L27/06 ,  H01L29/70 ,  H03K19/08 ,  H03K19/094 ,  H03K19/20 ,  H03K19/21

CPC classification number: H03K19/09418 ,  H01L27/0623

Abstract: An integrated logic circuit arrangement comprising: an input junction field effect transistor having at least one source for receiving a digital input signal, a drain to which a load is connected, and gate held at a reference potential, said junction field effect transistor being operative to effect switching operation in accordance with said digital input signal; and an output bipolar type transistor having its base connected to said drain to effect switching operation in accordance with an output signal delivered from said drain. This integrated logic circuit arrangement provides high speed logic operation, low power dissipation and high integration density.

Abstract translation: 一种集成逻辑电路装置，包括：输入结场效应晶体管，其具有用于接收数字输入信号的至少一个源极，连接负载的漏极和保持在参考电位的栅极，所述结型场效应晶体管可操作为 根据所述数字输入信号进行效果切换操作; 以及输出双极型晶体管，其基极连接到所述漏极，以根据从所述漏极输出的输出信号进行开关操作。 该集成逻辑电路布置提供高速逻辑运算，低功耗和高集成密度。

公开(公告)号：US4216038A

公开(公告)日：1980-08-05

申请号：US913006

申请日：1978-06-05

Applicant: Jun-ichi Nishizawa ,  Yasunori Mochida ,  Terumoto Nonaka ,  Tadahiko Hotta ,  Shin Yamashita

Inventor： Jun-ichi Nishizawa ,  Yasunori Mochida ,  Terumoto Nonaka ,  Tadahiko Hotta ,  Shin Yamashita

IPC: H01L29/80 ,  H01L21/033 ,  H01L29/739 ,  H01L21/22

CPC classification number: H01L29/739 ,  H01L21/033 ,  Y10S438/942

Abstract: In a semiconductor device of the type arranged so that the minority carriers are injected into a lightly-doped n type semiconductor layer from a heavily-doped p type semiconductor layer provided in the n type layer, that portion of the p type layer excluding a certain portion is separated from the n type layer by a separator layer to cause the p type layer to contact the n type layer only at the certain portion, whereby the carrier injection is restricted to occur within a limited region of the n type layer contacting the certain portion of the p type layer. The separator and the p type layer are formed, by relying on a self-alignment technique using a double-mask layer, as diffused regions partially overlapping each other with a good relative alignment in the n type layer.

Abstract translation: 在配置为使得少数载流子从设置在n型层中的重掺杂p型半导体层注入到轻掺杂n型半导体层中的类型的半导体器件中，除了一定的p型层之外的该部分 部分通过分隔层与n型层分离，使得p型层仅在某一部分与n型层接触，由此载流子注入被限制在n型层的有限区域内， p型层的一部分。 通过依靠使用双掩模层的自对准技术，形成分隔层和p型层，作为在n型层中以良好的相对取向部分地彼此重叠的扩散区域。

公开(公告)号：US4811254A

公开(公告)日：1989-03-07

申请号：US940545

申请日：1986-12-12

Applicant: Kenzaburou Iijima ,  Yuoshinori Hayashi ,  Terumoto Nonaka ,  Akira Usui

Inventor： Kenzaburou Iijima ,  Yuoshinori Hayashi ,  Terumoto Nonaka ,  Akira Usui

IPC: H03M1/00 ,  G06F15/36

CPC classification number: H03M1/0607 ,  H03M1/1019 ,  H03M1/303

Abstract: An absolute displacement detector utilizing two sensors and a code bearing track having domains arranged such that relative movement between the sensors and the track produces two signals in phase quadrature which are processed with digital circuitry to provide displacement data indicated by a multiple bit digital word whose higher bits indicate number of domains passed and whose lower bits indicate position within a domain.

Abstract translation: 使用两个传感器和代码承载轨道的绝对位移检测器，其具有布置成使得传感器和轨道之间的相对运动产生相位正交的两个信号，其中数字电路被处理以提供由多位数字字表示的位移数据， 位表示通过的域数，其低位表示域内的位置。

公开(公告)号：US4327623A

公开(公告)日：1982-05-04

申请号：US135700

申请日：1980-03-31

Applicant: Yasunori Mochida ,  Terumoto Nonaka ,  Osamu Hanagasaki

Inventor： Yasunori Mochida ,  Terumoto Nonaka ,  Osamu Hanagasaki

IPC: G10H1/44 ,  G10G7/02

CPC classification number: G10H1/44 ,  Y10S84/18

Abstract: A reference frequency generator for a tuning apparatus comprising a variable frequency divider which frequency divides a source signal in accordance with frequency division data stored in one or more ROM's. The frequency division data comprises note data for specifying frequencies of respective notes in one octave of a musical scale, pitch deviation data for specifying pitch deviation of the respective notes in one octave with respect to the frequencies specified by said note data and tuning curve data for specifying tuning characeristics covering several octaves, so that the generator generates reference frequency signals representing various pitch deviations and tuning characteristics as well as a standard tuning pitch or characteristic.

Abstract translation: 一种用于调谐装置的参考频率发生器，包括可变分频器，其根据存储在一个或多个ROM中的分频数据对源信号进行频率分频。 分频数据包括用于指定音阶的一个八度音阶中的各个音符的频率的音符数据，用于指定相对于由所述音符数据指定的频率的一个八度音阶中的各音符的音调偏差的音高偏差数据，以及用于 指定覆盖几个八度的调谐特征，使得发生器产生表示各种音调偏差和调谐特性以及标准调谐音调或特性的参考频率信号。

公开(公告)号：US4255671A

公开(公告)日：1981-03-10

申请号：US819405

申请日：1977-07-26

Applicant: Terumoto Nonaka ,  Takashi Yoshida ,  Takeshi Matsuyama

Inventor： Terumoto Nonaka ,  Takashi Yoshida ,  Takeshi Matsuyama

IPC: H01L29/80 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/02 ,  H01L27/06 ,  H01L27/07 ,  H01L29/73 ,  H03K19/094 ,  H01L27/04 ,  H03K19/091

CPC classification number: H01L27/024 ,  H01L27/0716

Abstract: In an integrated injection logic (IIL) type semiconductor integrated circuit, an injector transistor is formed with a field effect transistor (FET) and an inverter transistor is formed with a bipolar transistor (BPT). The drain region of the FET is merged into the base region of the BPT. The base of the BPT constitutes a logic input and the collector of the BPT constitutes a logic output. The FET may be either of the junction type or of the insulated gate type. The carrier injection efficiency can be improved to approximately unity over a wide range of the injection current.

Abstract translation: 在集成注入逻辑（IIL）型半导体集成电路中，注入晶体管形成有场效应晶体管（FET），反相晶体管由双极晶体管（BPT）形成。 FET的漏极区域合并到BPT的基极区域。 BPT的基础构成逻辑输入，BPT的收集器构成逻辑输出。 FET可以是结型或绝缘栅型中的任一种。 在较宽的注入电流范围内，载流子注入效率可以提高到近似一致。

公开(公告)号：US4150392A

公开(公告)日：1979-04-17

申请号：US820245

申请日：1977-07-29

Applicant: Terumoto Nonaka

Inventor： Terumoto Nonaka

IPC: G11C11/411 ,  G11C11/416 ,  G11C19/28 ,  H01L27/02 ,  H01L27/07 ,  H03K3/288

CPC classification number: H01L27/024 ,  G11C11/4113 ,  G11C11/4116 ,  G11C11/416 ,  G11C19/28 ,  H01L27/0711 ,  H03K3/288

Abstract: A semiconductor integrated circuit comprises a pair of load transistors and a pair of inverter transistors to constitute a flip-flop circuit. The load transistors are formed of p-channel field effect transistors serving as carrier injectors for the inverters formed of npn bipolar transistors. The p-type drain region of each load transistor is merged into the p-type base region of each inverter transistor. The absence of carrier storage effect in the field effect transistors improves the operation speed of the flip-flop remarkably and the high impedance gate electrode can be utilized as the clocking electrode to achieve clocking with voltage pulses without substantial power consumption. A plurality of such flip-flops are connected in cascode one after another to constitute a shift register.

Abstract translation: 半导体集成电路包括一对负载晶体管和一对逆变器晶体管，以构成触发电路。 负载晶体管由用作由npn双极晶体管形成的反相器的载流子注入器的p沟道场效应晶体管形成。 每个负载晶体管的p型漏极区域被合并到每个反相器晶体管的p型基极区域中。 在场效应晶体管中不存在载流子存储效应显着提高了触发器的操作速度，并且高阻抗栅电极可以用作时钟电极，以实现具有电压脉冲的时钟，而没有实质的功耗。 多个这样的触发器依次以级联连接以构成移位寄存器。

公开(公告)号：US4949275A

公开(公告)日：1990-08-14

申请号：US752934

申请日：1985-07-08

Applicant: Terumoto Nonaka

Inventor： Terumoto Nonaka

IPC: H01L21/822 ,  G06F17/50 ,  H01L21/82 ,  H01L27/02 ,  H01L27/04 ,  H01L27/118

CPC classification number: H01L27/118 ,  G06F17/5068 ,  H01L27/0207

Abstract: A semiconductor integrated circuit device comprises a semiconductor chip with a plurality of standard cells formed thereon. Each of said standard cells consists of at least one type of standard cell which is selected from among a plural types of standard cells which are pre-registered in a standard cell library retained by a computer. The placement and routing pattern of said standard cells on said semiconductor chip are designed automatically by a computer system. In relation to at least one of said standard cells, at least one basic cell for general-purpose logical gate is formed on said semiconductor chip to deal with design modification of the device.

Abstract translation: 半导体集成电路器件包括在其上形成有多个标准单元的半导体芯片。 所述标准单元中的每一个由至少一种类型的标准单元组成，所述标准单元选自预先登记在由计算机保留的标准单元库中的多种类型的标准单元。 所述半导体芯片上的所述标准单元的放置和布线图案由计算机系统自动设计。 关于至少一个所述标准单元，在所述半导体芯片上形成用于通用逻辑门的至少一个基本单元，以处理器件的设计修改。

公开(公告)号：US4806860A

公开(公告)日：1989-02-21

申请号：US59941

申请日：1987-06-09

Applicant: Kenzaburou Iijima ,  Yoshinori Hayashi ,  Terumoto Nonaka ,  Katsuyuki Yokoi ,  Seiya Nishimura

Inventor： Kenzaburou Iijima ,  Yoshinori Hayashi ,  Terumoto Nonaka ,  Katsuyuki Yokoi ,  Seiya Nishimura

IPC: G01D5/14 ,  G01D5/16 ,  G01P3/487 ,  G01P3/54 ,  G01B7/14 ,  G01R33/02 ,  H03K17/90 ,  H03K19/18

CPC classification number: G01D5/145 ,  G01P3/487 ,  G01P3/54

Abstract: A magnetoresistive detection head for detecting relative displacement of a magnetic recording medium relative to the detection head includes two sets of magnetoresistive elements which change their respective resistances in response to changes in the intensity of a magnetic field generated by the magnetic recording medium during the relative displacement. The magnetoresistive elements are overlapped and spaced relative to each other by a specified space lag in the direction of the relative displacement. One set of magnetoresistive elements produce a sine output and the other a cosine output. The overlapping and precise spacing of the elements aligns the phases of the signal envelopes of the sine and cosine outputs, reducing reading errors when physical warps appear on the magnetic recording medium.

Abstract translation: 用于检测磁记录介质相对于检测头的相对位移的磁阻检测头包括两组磁阻元件，它们响应于磁记录介质在相对位移期间产生的磁场强度的变化而改变其各自的电阻 。 磁阻元件在相对位移的方向上相对于彼此重叠并间隔规定的空间滞后。 一组磁阻元件产生正弦输出，另一组产生余弦输出。 元件的重叠和精确的间距使正弦和余弦输出的信号包络的相位对齐，从而在磁记录介质上出现物理翘曲时减少读取误差。