公开(公告)号：US06850120B2

公开(公告)日：2005-02-01

申请号：US10308058

申请日：2002-12-03

申请人： Tetsuya Heima ,  Hiroshi Komurasaki

发明人： Tetsuya Heima ,  Hiroshi Komurasaki

IPC分类号： H03F1/22 ,  H03F3/193

CPC分类号： H03F1/223 ,  H03F3/193

摘要： A first NMOS transistor has its source connected to ground and its drain connected to the source of a second NMOS transistor of high breakdown voltage via an inductor. The second NMOS transistor of high breakdown voltage has its drain connected to a power supply line Vdd via the inductor. An output Vout is provided from the drain of the second NMOS transistor. When an input voltage Vin is applied to the gate of the first NMOS transistor and a bias voltage Vg2 is applied to the gate of the second NMOS transistor, the first and second NMOS transistors operate. The voltage amplitude of the load end of the second NMOS transistor of high breakdown voltage connected to the inductor swings about the power supply voltage. The voltage amplitude increases as the output voltage becomes higher.

摘要翻译： 第一NMOS晶体管的源极连接到地，其漏极通过电感器连接到具有高击穿电压的第二NMOS晶体管的源极。 高击穿电压的第二个NMOS晶体管的漏极通过电感连接到电源线Vdd。 从第二NMOS晶体管的漏极提供输出Vout。 当输入电压Vin施加到第一NMOS晶体管的栅极并且偏置电压Vg2施加到第二NMOS晶体管的栅极时，第一和第二NMOS晶体管工作。 连接到电感器的高击穿电压的第二NMOS晶体管的负载端的电压幅度围绕电源电压摆动。 电压幅度随着输出电压变高而增加。

公开(公告)号：US06177841B1

公开(公告)日：2001-01-23

申请号：US09258069

申请日：1999-02-26

申请人： Akira Ohta ,  Akira Inoue ,  Tetsuya Heima

发明人： Akira Ohta ,  Akira Inoue ,  Tetsuya Heima

IPC分类号： H03F3191

CPC分类号： H03F3/601 ,  H01L2224/48091 ,  H03F1/0205 ,  H03F1/565 ,  H01L2924/00014

摘要： A high frequency power amplifier with reduced power loss and improved power amplification efficiency has an output matching circuit providing an open circuit to a second harmonic and a short circuit to a third harmonic of a high frequency signal. This is accomplished by, for example, adjusting lengths of a drain bias line and a plurality of signal lines so that the phase of S parameter S11 (input reflection coefficient) to the second harmonic is from −80° to 140°, and the phase of S parameter S11 to the third harmonic is from 160° to 220°. The line length of each line in an input matching circuit is also adjusted so that the phase of S parameter S22 (output reflection coefficient) at the fundamental frequency is between +5° to −75°.

摘要翻译： 具有降低的功率损耗和提高的功率放大效率的高频功率放大器具有输出匹配电路，其提供对二次谐波的开路和与高频信号的三次谐波的短路。 这通过例如调整漏极偏置线和多条信号线的长度来实现，使得S参数S11（输入反射系数）相对于二次谐波的相位为-80°至140°，相位 S参数S11与三次谐波的关系为160°〜220°。 也调整输入匹配电路中每条线的线路长度，使得基频下的S参数S22（输出反射系数）的相位在+ 5°至-75°之间。

公开(公告)号：US5834960A

公开(公告)日：1998-11-10

申请号：US880767

申请日：1997-06-23

申请人： Tetsuya Heima ,  Norio Higashisaka ,  Akira Ohta

发明人： Tetsuya Heima ,  Norio Higashisaka ,  Akira Ohta

IPC分类号： H03H11/26 ,  H03K5/13

CPC分类号： H03K5/133 ,  H03H11/265 ,  H03K5/131

摘要： A semiconductor device includes an input terminal and an output terminal; a delay circuit including N (N=integer) unit delay circuits connected in series between the input terminal and the output terminal, earn unit delay circuit including first and second two-input NOR or NAND circuits connected in series, the second two-input NOR or NAND circuit being nearer to the output terminal than the first two-input NOR or NAND circuit, a first input of each first two-input NOR or NAND circuit being connected to the input terminal, and an output of each first two-input NOR or NAND circuit being connected to a first input of the second two-input NOR or NAND circuit of each unit delay circuit; and a control circuit outputting individual control signals, each control signal being applied to a respective second input of the second two-input NOR or NAND circuit included in each unit delay circuit, wherein delay time in signal transmission from the input terminal to the output terminal varies in response to the control signals. The number of elements per unit resolution is reduced, and variations in the delay time are reduced by the reduced element number so the linearity of the delay circuit is improved. Further, the layout is simplified as compared with the conventional delay circuit.

摘要翻译： 半导体器件包括输入端子和输出端子; 包括在输入端子和输出端子之间串联连接的N（N =整数）个单位延迟电路的延迟电路，包括串联连接的第一和第二双输入NOR或NAND电路的单位延迟电路，第二双输入NOR 或NAND电路比第一双输入NOR或NAND电路更接近输出端，每个第一双输入NOR或NAND电路的第一输入连接到输入端，并且每个第一双输入NOR 或NAND电路连接到每个单位延迟电路的第二双输入NOR或NAND电路的第一输入; 以及输出各个控制信号的控制电路，每个控制信号被施加到包括在每个单位延迟电路中的第二双输入NOR或NAND电路的相应的第二输入，其中从输入端到输出端的信号传输的延迟时间 响应于控制信号而变化。 降低了每单位分辨率的元件数量，并且通过减少元件数量来减小延迟时间的变化，从而提高了延迟电路的线性度。 此外，与传统的延迟电路相比，布局被简化。

公开(公告)号：US20120146740A1

公开(公告)日：2012-06-14

申请号：US13309350

申请日：2011-12-01

申请人： Yoshikazu FURUTA ,  Tetsuya Heima ,  Kazuaki Hori

发明人： Yoshikazu FURUTA ,  Tetsuya Heima ,  Kazuaki Hori

IPC分类号： H03C3/02 ,  H03H7/00

CPC分类号： H04B1/0475 ,  H04B1/30

摘要： The present invention provides a semiconductor device. In the semiconductor device, a signal distributor distributes a high frequency signal generated by an oscillator and inputted to an input part to first and second signals and outputs the same from first and second output parts respectively. A modulator modulates a baseband signal with the first signal and outputs the same therefrom. An offset adjustment unit compares the second signal and the first signal that leaks from the output of the modulator to thereby adjust an offset of the baseband signal. The signal distributor includes a first capacitive element provided between the input part and the first output part, and a second capacitive element provided between the first output part and the second output part. The electrostatic capacitance of the first capacitive element is larger than that of the second capacitive element.

摘要翻译： 本发明提供一种半导体器件。 在半导体器件中，信号分配器分配由振荡器产生的高频信号并将其输入到输入部分到第一和第二信号，并且分别从第一和第二输出部分输出。 A调制器用第一个信号调制基带信号并输出​​相同的信号。 偏移调整单元将第二信号和从调制器的输出泄漏的第一信号进行比较，从而调整基带信号的偏移。 信号分配器包括设置在输入部分和第一输出部分之间的第一电容元件和设置在第一输出部分和第二输出部分之间的第二电容元件。 第一电容元件的静电电容大于第二电容元件的静电电容。

公开(公告)号：US20110142113A1

公开(公告)日：2011-06-16

申请号：US12963385

申请日：2010-12-08

申请人： Mitsuhiko HOKAZONO ,  Tetsuya Heima ,  Kazuaki Hori

发明人： Mitsuhiko HOKAZONO ,  Tetsuya Heima ,  Kazuaki Hori

IPC分类号： H04L27/36 ,  H04B17/00

CPC分类号： H04L27/0014 ,  H03D7/1441 ,  H03D7/1458 ,  H04L27/362 ,  H04L2027/0018

摘要： The present invention provides a communication apparatus (RFIC) capable of performing a DC offset correction of an orthogonal modulation unit with a degree of accuracy higher than conventional. The orthogonal modulation unit of the RFIC includes first and second mixers, an adder and first and second switches. The first mixer receives a first local oscillation signal therein through the first switch. The second mixer receives a second local oscillation signal therein through the second switch. During calibration, a DC offset of the first mixer is adjusted in a state in which the first switch is brought to an ON state and the second switch is brought to an OFF state. Further, a DC offset of the second mixer is adjusted in a state in which the first switch is brought to an OFF state and the second switch is brought to an ON state.

摘要翻译： 本发明提供一种能够以比常规更高的精度执行正交调制单元的DC偏移校正的通信装置（RFIC）。 RFIC的正交调制单元包括第一和第二混频器，加法器和第一和第二开关。 第一混频器通过第一开关接收第一本地振荡信号。 第二混频器通过第二开关接收第二本地振荡信号。 在校准期间，在第一开关处于导通状态并使第二开关处于断开状态的状态下调节第一混合器的直流偏移。 此外，在第一开关处于断开状态并且第二开关变为导通状态的状态下调节第二混合器的DC偏移。

公开(公告)号：US06894598B2

公开(公告)日：2005-05-17

申请号：US10614610

申请日：2003-07-08

申请人： Tetsuya Heima

发明人： Tetsuya Heima

IPC分类号： H01F30/00 ,  H01F17/00 ,  H01F27/34 ,  H01L21/822 ,  H01L27/04 ,  H01L27/08 ,  H01M5/00

CPC分类号： H01F17/0013 ,  H01F27/34 ,  H01L27/08

摘要： An inductor has a laminated structure in which an insulating layer and a wiring layer are laminated alternately on a semiconductor substrate. The laminated structure includes at least two wiring layers and an insulating layer interposed between them. A first wiring layer has a first winding part and a second winding part in the same plane, adjacent each other, and wound. A second wiring layer has a wiring part having a single path from one terminal to the other. The first and second winding parts are electrically connected to the wiring part. When a voltage is applied between one terminal of the first winding part and one terminal of the second winding part, currents flow in the first and second winding parts in opposite directions.

摘要翻译： 电感器具有层叠结构，其中绝缘层和布线层交替层叠在半导体衬底上。 叠层结构包括至少两个布线层和介于它们之间的绝缘层。 第一布线层在同一平面上具有彼此相邻并缠绕的第一绕组部分和第二绕组部分。 第二布线层具有从一个端子到另一个端子的单一路径的布线部分。 第一和第二绕组部分电连接到布线部分。 当在第一绕组部分的一个端子和第二绕组部分的一个端子之间施加电压时，电流在相反的方向上在第一和第二绕组部件中流动。

公开(公告)号：US5859554A

公开(公告)日：1999-01-12

申请号：US773234

申请日：1996-12-23

申请人： Norio Higashisaka ,  Akira Ohta ,  Tetsuya Heima

发明人： Norio Higashisaka ,  Akira Ohta ,  Tetsuya Heima

IPC分类号： H03K5/131 ,  H03K5/14 ,  H03K5/13

CPC分类号： H03K5/131

摘要： A variable delay circuit that delays an input signal for a desired time and outputs the delayed signal includes N (N is an integer of 2 or more) load transistors and N control transistors for controlling the load transistors respectively connected in pairs in series to form N load transistor pairs. The load transistor pairs are connected in parallel to form a load transistor group. A switching transistor that is turned on or off according to an input signal input to a gate, and the load transistor group are connected in series between first and second power supplies. The input signal is delayed according to control signals that are respectively input to the control transistors, and a delayed signal is output from a connection node of the load transistor group and the switching transistor. Since no selector is required, a delay circuit operation due to differences in delay times between paths in a selector is avoided, thereby obtaining a variable delay circuit having minute resolution and a good yield.

摘要翻译： 将输入信号延迟所需时间并输出延迟信号的可变延迟电路包括负载晶体管的N（N为2以上的整数）和用于控制分别成对串联连接的负载晶体管的N个控制晶体管，形成N 负载晶体管对。 负载晶体管对并联连接形成负载晶体管组。 根据输入到栅极的输入信号导通或截止的开关晶体管，负载晶体管组串联连接在第一和第二电源之间。 输入信号根据分别输入到控制晶体管的控制信号进行延迟，延迟信号从负载晶体管组和开关晶体管的连接节点输出。 由于不需要选择器，所以避免了由于选择器中的路径之间的延迟时间的差异导致的延迟电路操作，从而获得具有微小分辨率和良好产量的可变延迟电路。

公开(公告)号：US5821793A

公开(公告)日：1998-10-13

申请号：US695575

申请日：1996-08-12

申请人： Akira Ohta ,  Norio Higashisaka ,  Tetsuya Heima

发明人： Akira Ohta ,  Norio Higashisaka ,  Tetsuya Heima

IPC分类号： H03K5/06 ,  H03K3/03 ,  H03K3/354 ,  H03K5/14 ,  H03K5/13 ,  H03K7/08

CPC分类号： H03K5/133 ,  H03K5/131

摘要： A variable delay circuit including an input terminal to which a signal to be delayed is input, a delay gate connected to the input terminal, a logical gate to which an input to the delay gate and an output from the delay gate are input and which forms a delayed signal, and an output terminal outputting the delayed signal formed by the logical gate. A control signal for controlling the delay gate is input to the delay gate.

摘要翻译： 一个可变延迟电路，包括一个输入端子，输入一个待延迟信号的输入端子，连接到输入端子的延迟栅极，输入到延迟门的输入端和延迟门的输出端的逻辑门， 延迟信号，以及输出由逻辑门形成的延迟信号的输出端子。 用于控制延迟门的控制信号被输入到延迟门。