公开(公告)号：US07453302B2

公开(公告)日：2008-11-18

申请号：US10744807

申请日：2003-12-23

申请人： Thoai Thai Le ,  Jung Pill Kim

发明人： Thoai Thai Le ,  Jung Pill Kim

IPC分类号： H03H11/26

CPC分类号： H03K5/133 ,  G11C7/04 ,  G11C7/22 ,  G11C7/222 ,  H03K2005/00143 ,  H03K2005/00156

摘要： A temperature compensated delay circuit for delaying a signal within an integrated circuit includes a temperature sensor. The temperature sensor is configured to sense a temperature proximal to the integrated circuit and configured to provide a control signal representative of the sensed temperature proximal to the integrated circuit. A delay chain is configured to receive a signal and provide a plurality of output signals. Each output signal has a time delay distinct from other output signals. A multiplexer is configured to receive the plurality of output signals from the delay chain and to receive the control signal from the temperature sensor representative of the sensed temperature. The multiplexer is configured to provide a temperature compensated delayed output signal.

摘要翻译： 用于延迟集成电路内的信号的温度补偿延迟电路包括温度传感器。 温度传感器被配置为感测靠近集成电路的温度并且被配置为提供表示接近集成电路的感测温度的控制信号。 延迟链被配置为接收信号并提供多个输出信号。 每个输出信号具有与其他输出信号不同的时间延迟。 多路复用器被配置为从延迟链接收多个输出信号并且接收来自表示感测温度的温度传感器的控制信号。 多路复用器被配置为提供温度补偿的延迟输出信号。

公开(公告)号：US06956786B2

公开(公告)日：2005-10-18

申请号：US10727406

申请日：2003-12-04

申请人： Torsten Partsch ,  Thoai Thai Le

发明人： Torsten Partsch ,  Thoai Thai Le

IPC分类号： G11C8/00 ,  G11C29/00

CPC分类号： G11C29/883 ,  G11C11/401 ,  G11C29/816 ,  G11C29/88

摘要： A random access memory comprises a plurality of data pads and an array of memory cells comprising a first portion of memory cells and a second portion of memory cells. The random access memory comprises a first line configured to receive first data signals between the first portion of memory cells and the data pads and a second line configured to receive second data signals between the second portion of memory cells and the data pads. The first portion of memory cells is configured to be made inaccessible to eliminate the first data signals and a first number of the data pads and the second portion of memory cells is configured to be made inaccessible to eliminate the second data signals and a second number of the data pads.

摘要翻译： 随机存取存储器包括多个数据焊盘和包括存储器单元的第一部分和存储器单元的第二部分的存储单元阵列。 随机存取存储器包括被配置为在存储器单元的第一部分和数据焊盘之间接收第一数据信号的第一线和被配置为在第二部分存储器单元和数据焊盘之间接收第二数据信号的第二线。 存储器单元的第一部分被配置为不可访问以消除第一数据信号，并且第一数量的数据焊盘和第二部分存储器单元被配置为不可访问以消除第二数据信号和第二数量的 数据垫。

公开(公告)号：US06756655B2

公开(公告)日：2004-06-29

申请号：US10013298

申请日：2001-12-10

申请人： Thoai-Thai Le ,  Jürgen Lindolf

发明人： Thoai-Thai Le ,  Jürgen Lindolf

IPC分类号： H01L2900

CPC分类号： H01L23/5256 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor configuration is described which includes a semiconductor body having a main surface and an insulator layer disposed on the main surface of the semiconductor body. The insulator layer has a cavity formed therein extending to the main surface of the semiconductor body. A fuse having a fusible part extends from the main surface of the semiconductor body toward an upper surface of the insulator layer at right angles to the main surface of the semiconductor body, and the fuse is embedded in the cavity. A method for producing the semiconductor configuration having the fuse is also described.

摘要翻译： 描述了一种半导体结构，其包括具有设置在半导体主体的主表面上的主表面和绝缘体层的半导体本体。 绝缘体层具有形成在其中的空腔，其延伸到半导体本体的主表面。 具有可熔部分的保险丝从半导体本体的主表面朝着与半导体主体的主表面成直角的绝缘体层的上表面延伸，并且保险丝嵌入在腔中。 还描述了具有熔丝的半导体结构的制造方法。

公开(公告)号：US07518231B2

公开(公告)日：2009-04-14

申请号：US11203861

申请日：2005-08-15

申请人： James Dietz ,  Petros Negussu ,  Thoai Thai Le

发明人： James Dietz ,  Petros Negussu ,  Thoai Thai Le

IPC分类号： H01L23/12

CPC分类号： H01L25/0657 ,  H01L24/45 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A multi-chip package comprising at least a first die and a second die, wherein each die comprises an integrated circuit (IC) disposed thereon. Each of the first die and the second die comprise a plurality of contact pads coupled with the respective IC. The contact pads on the first IC comprise a first mode pad coupled to a first device formed on the first die, and the contact pads on the second IC comprise a second mode pad coupled to a second device formed on the second die. The first mode pad is coupled to a first potential and causes the first device to operate in a first mode. The second mode pad is coupled to a second potential and causes the second device to operate in a second mode. The first and second mode are selected based on the relative position of the first and second die.

摘要翻译： 一种包括至少第一管芯和第二管芯的多芯片封装，其中每个管芯包括设置在其上的集成电路（IC）。 第一管芯和第二管芯中的每一个包括与相应的IC耦合的多个接触焊盘。 第一IC上的接触焊盘包括耦合到形成在第一裸片上的第一器件的第一模式焊盘，并且第二IC上的接触焊盘包括耦合到形成在第二裸片上的第二器件的第二模式焊盘。 第一模式焊盘耦合到第一电位并使第一器件以第一模式工作。 第二模式焊盘耦合到第二电位并使第二装置在第二模式下操作。 基于第一和第二管芯的相对位置来选择第一和第二模式。

公开(公告)号：US06970395B2

公开(公告)日：2005-11-29

申请号：US10658130

申请日：2003-09-08

申请人： Thoai-Thai Le ,  Ralf Klein ,  Eckhard Brass ,  George Alexander

发明人： Thoai-Thai Le ,  Ralf Klein ,  Eckhard Brass ,  George Alexander

IPC分类号： G11C7/10 ,  G11C11/4076 ,  G11C8/00

CPC分类号： G11C11/4076 ,  G11C7/1051 ,  G11C7/1072 ,  G11C2207/2281

摘要： A memory device includes a delay-locked loop circuit having delay elements and a synchronization circuit coupled to the delay-locked loop circuit. The synchronization circuit receives a synchronization enable signal and outputs a plurality of enable signals, including an enable signal coupled to an output circuit. Because the enable signal is synchronized with the read signal, it is possible to provide more time to read data into the buffer. A method of reading data from a memory device couples a synchronization enable signal and an external clock signal to a synchronization circuit. A read signal and an output enable are generated based upon a synchronization enable signal and a delayed clock signal of the external clock signal. Because the output signal is synchronized to the read signal, more time is allowed for the sense function.

摘要翻译： 存储器件包括具有延迟元件的延迟锁定环路电路和耦合到延迟锁定环路电路的同步电路。 同步电路接收同步使能信号并输出​​多个使能信号，包括耦合到输出电路的使能信号。 由于使能信号与读取信号同步，所以可以提供更多的时间将数据读入缓冲器。 从存储器件读取数据的方法将同步使能信号和外部时钟信号耦合到同步电路。 基于外部时钟信号的同步使能信号和延迟的时钟信号，产生读取信号和输出使能。 由于输出信号与读取信号同步，所以允许感应功能更多的时间。

公开(公告)号：US06389086B1

公开(公告)日：2002-05-14

申请号：US09521396

申请日：2000-03-08

申请人： Thoai-Thai Le ,  Eckhard Brass ,  Markus Biebl

发明人： Thoai-Thai Le ,  Eckhard Brass ,  Markus Biebl

IPC分类号： H03B110

CPC分类号： H03K5/1252

摘要： A digital circuit has a signal input terminal and a signal output terminal. The digital circuit additionally has a logic circuit unit, whose input is connected to the signal input terminal and whose output is connected to the signal output terminal via a switching element. Furthermore, it has a filter unit, whose input is connected to the signal input terminal and whose output is connected to a control input of the switching element. The filter unit serves for suppressing glitches on a digital signal present at its input.

摘要翻译： 数字电路具有信号输入端和信号输出端。 数字电路还具有逻辑电路单元，其输入端连接到信号输入端子，其输出端经由开关元件连接到信号输出端子。 此外，它具有滤波器单元，其输入端连接到信号输入端，并且其输出端连接到开关元件的控制输入端。 滤波器单元用于抑制存在于其输入端的数字信号的毛刺。

公开(公告)号：US06838917B2

公开(公告)日：2005-01-04

申请号：US10266354

申请日：2002-10-07

申请人： Eckhard Brass ,  Bernd Klehn ,  Ralf Klein ,  Thoai-Thai Le

发明人： Eckhard Brass ,  Bernd Klehn ,  Ralf Klein ,  Thoai-Thai Le

IPC分类号： G11C7/10 ,  G11C7/22 ,  H03L7/06

CPC分类号： G11C7/1066 ,  G11C7/04 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222

摘要： A circuit configuration for processing data, particularly a semiconductor memory chip, has a control circuit for setting a phase or frequency relationship between two signals. A digital counter detects a phase or frequency difference between the two signals, and the counter reading is used for regulating the phase or frequency relationship. Trials have shown that the counter reading indicates an operating state in the circuit configuration and therefore represents a simple signal for assessing the operating state of the circuit configuration. Preferably, the counter reading is taken as a basis for adjusting the speed or power of time-critical or performance-critical circuit parts in the circuit configuration so that an operating state with an intermediate switching speed is obtained.

摘要翻译： 用于处理数据的电路配置，特别是半导体存储器芯片，具有用于设置两个信号之间的相位或频率关系的控制电路。 数字计数器检测两个信号之间的相位或频率差，并且计数器读数用于调节相位或频率关系。 试验表明，计数器读数表示电路配置中的工作状态，因此表示用于评估电路配置工作状态的简单信号。 优选地，计数器读数作为调整电路配置中时间关键或性能关键电路部件的速度或功率的基础，从而获得具有中间切换速度的操作状态。

公开(公告)号：US06717447B1

公开(公告)日：2004-04-06

申请号：US10271955

申请日：2002-10-15

申请人： Thoai-Thai Le ,  Ralf Klein

发明人： Thoai-Thai Le ,  Ralf Klein

IPC分类号： H03L700

CPC分类号： H03L7/0814 ,  H03K2005/00058 ,  H03K2005/00234

摘要： A delay adjustment circuit for decreasing a phase shift between a system clock and a feedback clock from a semiconductor's internal clock. The circuit includes a difference-pulse generator that provides an interim clock 180 degrees out of phase with the feedback clock when the feedback clock is leading the system clock, and equal to the feedback clock otherwise. The difference-pulse generator also provides a difference-pulse signal that is at logic high for a period of time by which the system clock and an inversion of the interim clock are phase shifted. The circuit also includes a delay control unit and a delay unit which delay the interim clock by the period of time. The resulting delayed interim clock, which is 180 degrees out of phase with the system clock, is inverted to provide an internal clock in phase with the system clock.

摘要翻译： 一种延迟调整电路，用于减少来自半导体内部时钟的系统时钟和反馈时钟之间的相移。 电路包括差分脉冲发生器，当反馈时钟引导系统时钟时，差分脉冲发生器提供与反馈时钟180度异相的中间时钟，否则等于反馈时钟。 差分脉冲发生器还提供在一段时间内处于逻辑高的差分脉冲信号，通过该时间段，系统时钟和中间时钟的反相相移。 该电路还包括一个延迟控制单元和延迟单元，该延迟单元将临时时钟延迟一段时间。 所产生的与系统时钟相差180度的延迟中间时钟被反相，以提供与系统时钟同相的内部时钟。

公开(公告)号：US06717200B1

公开(公告)日：2004-04-06

申请号：US09408688

申请日：1999-09-30

申请人： Florian Schamberger ,  Helmut Schneider ,  Jürgen Lindolf ,  Thoai-Thai Le

发明人： Florian Schamberger ,  Helmut Schneider ,  Jürgen Lindolf ,  Thoai-Thai Le

IPC分类号： H01L31119

CPC分类号： H01L29/66666 ,  H01L21/26586 ,  H01L29/42368 ,  H01L29/7827

摘要： A vertical MOS field effect transistor includes a gate disposed in a trench, a channel, and a source and a drain disposed in the substrate on the trench wall. The gate annularly surrounds a drain terminal which extends from the substrate surface as far as the drain disposed on the trench bottom. It is possible to produce vertical transistors with different channel lengths on a substrate with trenches of different widths by employing oblique implantation when producing the gate. A method of producing the vertical field effect transistor is also provided.

摘要翻译： 垂直MOS场效应晶体管包括设置在沟槽中的栅极，沟道以及设置在沟槽壁上的衬底中的源极和漏极。 栅极环形地围绕从衬底表面延伸到漏极设置在沟槽底部的漏极端子。 通过在制造栅极时采用倾斜注入，可以在具有不同宽度的沟槽的衬底上制造具有不同沟道长度的垂直晶体管。 还提供了一种制造垂直场效应晶体管的方法。

公开(公告)号：US06642804B2

公开(公告)日：2003-11-04

申请号：US10074578

申请日：2002-02-13

申请人： Ioannis Chrissostomidis ,  Thoai-Thai Le

发明人： Ioannis Chrissostomidis ,  Thoai-Thai Le

IPC分类号： H03L700

CPC分类号： H03K3/0231 ,  H03K3/011

摘要： The invention creates an oscillator circuit, in particular for a refresh timer device of a dynamic semiconductor memory, having a capacitor device (C; C′) which is connected between a first node (6) and a first supply potential (P2); a current mirror circuit (T1; T2) for supplying a charging current for the capacitor device (C; C′) which is connected via a first transistor device (T4) to the first node (6) and which has a current source (SQ) for supplying a substantially temperature-independent reference current (Iref); a second transistor device (T5), which is connected between the first node (6) and the first supply potential (P2); the first and second transistor devices (T4; T5) and a control signal being configured in such a way that the capacitor device (C; C′) can be charged via the first node (6) when a potential (Vcomp) at the first node (6) is lower than the reference potential (Vref), and can be discharged via the first node (6) when the potential (Vcomp) at the first node (6) is higher than the reference potential (Vref) such that the signal at an output (A) oscillates.

摘要翻译： 本发明创建了一种振荡器电路，特别是用于动态半导体存储器的刷新定时器装置，其具有连接在第一节点（6）和第一电源电位（P2）之间的电容器装置（C; C'）; 用于为经由第一晶体管器件（T4）连接到第一节点（6）并且具有电流源（SQ）的电容器器件（C; C'）提供充电电流的电流镜电路（T1; T2） ），用于提供基本上温度无关的参考电流（Iref）; 连接在第一节点（6）和第一电源电位（P2）之间的第二晶体管器件（T5）; 第一和第二晶体管器件（T4; T5）和控制信号被配置成使得当第一和第二晶体管器件（T4; T5）的电位（V comp） 节点（6）低于参考电位（Vref），并且当第一节点（6）处的电位（Vcomp）高于参考电位（Vref）时，可以经由第一节点（6）放电， 输出（A）的信号振荡。