公开(公告)号：US5877529A

公开(公告)日：1999-03-02

申请号：US978667

申请日：1997-11-26

Applicant: Koon Chong So ,  Danny Chi Nim ,  Fwu-Iuan Hshieh ,  Yan Man Tsui ,  True-Lon Lin ,  Shu-Hui Cheng

Inventor： Koon Chong So ,  Danny Chi Nim ,  Fwu-Iuan Hshieh ,  Yan Man Tsui ,  True-Lon Lin ,  Shu-Hui Cheng

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76 ,  H01L23/58 ,  H01L29/94

CPC classification number: H01L29/1095 ,  H01L29/0619 ,  H01L29/7811 ,  H01L29/0696 ,  H01L2924/0002

Abstract: Improved power MOSFET structure, and fabrication process are disclosed in this invention to achieve higher breakdown voltage and improved device ruggedness. The power transistor includes a core cell area which includes a plurality of power transistor cells and a termination area. The power transistor further includes an outer pickup guarding ring, disposed in the termination area guarding the core cell area, for picking up free charged-particles generated in the termination area for preventing the free charged particles from entering the core cell area. In another preferred embodiment, the power transistor further includes an inner pickup guarding fence and blocks, disposed between the termination area and the core cell area for picking up free charged-particles not yet picked up by the outer pickup guarding ring for preventing the free charged particles from entering the core cell area.

Abstract translation: 在本发明中公开了改进的功率MOSFET结构和制造工艺，以实现更高的击穿电压和改进的器件耐用性。 功率晶体管包括包含多个功率晶体管单元和端接区域的核心单元区域。 功率晶体管还包括外部拾波器保护环，设置在保护核心单元区域的端接区域中，用于拾取终止区域中产生的免费带电粒子，以防止自由带电粒子进入核心单元区域。 在另一个优选实施例中，功率晶体管还包括内部拾取器防护栅栏和块，其设置在终端区域和核心单元区域之间，用于拾取由外部拾音器保护环尚未拾取的免费带电粒子，以防止自由充电 颗粒进入核心区域。

公开(公告)号：US06919168B2

公开(公告)日：2005-07-19

申请号：US10057674

申请日：2002-01-24

Applicant: Jeng H. Hwang ,  Steve S. Y. Mak ,  True-Lon Lin ,  Chentsau Ying ,  John W. Schaller

Inventor： Jeng H. Hwang ,  Steve S. Y. Mak ,  True-Lon Lin ,  Chentsau Ying ,  John W. Schaller

IPC: C23F4/00 ,  H01L21/02 ,  H01L21/3213 ,  G03F7/00 ,  G03F7/36

CPC classification number: H01L28/60 ,  C23F4/00 ,  H01L21/32136 ,  H01L21/32139

Abstract: A method of etching a noble metal electrode layer disposed on a substrate to produce a semiconductor device including a plurality of electrodes separated by a distance equal to or less than about 0.35 μm and having a noble metal profile equal to or greater than about 80°. The method comprises heating the substrate to a temperature greater than about 150° C., and etching the noble metal electrode layer by employing a high density inductively coupled plasma of an etchant gas comprising a gas selected from the group consisting of nitrogen, oxygen, a halogen (e.g., chlorine), argon, and a gas selected from the group consisting of BCl3, HBr, and SiCl4 mixtures thereof. Masking methods and etching sequences for patterning high density RAM capacitors are also provided.

Abstract translation: 一种蚀刻设置在基板上的贵金属电极层的方法，以制造半导体器件，该半导体器件包括间隔等于或小于约0.35μm并且具有等于或大于约80°的贵金属形状的多个电极。 该方法包括将衬底加热到​​大于约150℃的温度，并且通过采用蚀刻剂气体的高密度电感耦合等离子体蚀刻贵金属电极层，所述等离子体包括选自氮，氧， 卤素（例如氯），氩气和选自BCl 3，HBr和SiCl 4+混合物的气体。 还提供了用于图案化高密度RAM电容器的掩模方法和蚀刻顺序。

公开(公告)号：US06734452B2

公开(公告)日：2004-05-11

申请号：US09825875

申请日：2001-04-03

Applicant: Sarath Gunapala ,  John K. Liu ,  Jin S. Park ,  True-Lon Lin ,  Mani Sundaram

Inventor： Sarath Gunapala ,  John K. Liu ,  Jin S. Park ,  True-Lon Lin ,  Mani Sundaram

IPC: H01L2906

CPC classification number: B82Y20/00 ,  G01J5/28 ,  H01L31/035236 ,  Y10S977/759 ,  Y10S977/761 ,  Y10S977/915 ,  Y10S977/927

Abstract: An AlxGa1−xAs/GaAs/AlxGa1−xAs quantum well exhibiting a bound-to-quasibound intersubband absorptive transition is described. The bound-to-quasibound transition exists when the first excited state has the same energy as the “top” (i.e., the upper-most energy barrier) of the quantum well. The energy barrier for thermionic emission is thus equal to the energy required for intersubband absorption. Increasing the energy barrier in this way reduces dark current. The amount of photocurrent generated by the quantum well is maintained at a high level.

Abstract translation: 描述了表现出界限对准的子带间吸收转变的Al x Ga 1-x As / GaAs / Al x Ga 1-x As量子阱。 当第一激发态具有与量子阱的“顶部”（即，最上面的能量势垒）相同的能量时，存在边界到准近渡的转变。 因此，热离子发射的能量势垒等于子带间吸收所需的能量。 以这种方式增加能量屏障可以减少暗电流。 由量子阱产生的光电流的量保持在高水平。

公开(公告)号：US6104060A

公开(公告)日：2000-08-15

申请号：US603638

申请日：1996-02-20

Applicant: Fwu-Iuan Hshieh ,  True-Lon Lin

Inventor： Fwu-Iuan Hshieh ,  True-Lon Lin

IPC: H01L21/336 ,  H01L29/78 ,  H01L27/108 ,  H01L23/58 ,  H01L29/76

CPC classification number: H01L29/66712 ,  H01L23/3171 ,  H01L29/7811 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/402 ,  H01L2924/0002

Abstract: Improved power MOSFET structure, and fabrication process are disclosed in this invention to achieve cost savings by simplified device structure and fabrication processes, and also by reducing the required die size. Specifically, in a novel MOSFET device, insulation of mobile ions are achieved by extending the poly gate and metal contacts such that the passivation layer is no longer required and the fabrication process is simplified such that the MOSFET device can be manufactured at a lower price. Furthermore, in another MOSFET device, the gate runner is used to replace the field plate such that the requirement of a field plate as that in a conventional MOSFET device is also eliminated and, by reducing the die size, the cost of manufacture is further reduced.

Abstract translation: 在本发明中公开了改进的功率MOSFET结构和制造工艺，以通过简化的器件结构和制造工艺以及通过减少所需的管芯尺寸来实现成本节约。 具体地说，在新颖的MOSFET器件中，通过延长多晶硅栅极和金属触点来实现移动离子的绝缘，从而不再需要钝化层，并且简化了制造工艺，使得可以以更低的价格制造MOSFET器件。 此外，在另一个MOSFET器件中，栅极流道用于替代现场板，使得现场板的需求与常规MOSFET器件中的要求也被消除，并且通过减小管芯尺寸，制造成本进一步降低 。

公开(公告)号：US5986304A

公开(公告)日：1999-11-16

申请号：US782368

申请日：1997-01-13

Applicant: Fwu-Iuan Hshieh ,  Koon Chong So ,  True-Lon Lin

Inventor： Fwu-Iuan Hshieh ,  Koon Chong So ,  True-Lon Lin

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76

CPC classification number: H01L29/7813 ,  H01L29/4236 ,  H01L29/4238

Abstract: The present invention includes a substrate of a first conductivity type having a top surface including at least two intersecting trenches disposed therein with an insulating layer lining the trenches and a conductive material filling the trenches. The transistor also includes a source region of the first conductivity type extending from the top surface of the substrate adjacent to the trenches toward the substrate. The transistor further has a body region of a second conductivity type of opposite polarity from the first conductivity type, the body region extends from the top surface adjacent from the trenches to the substrate and surrounding the source region. The conductive material filling the trenches including punch-through suppressing blocks covering corners of the cell defined by the intersecting trenches wherein the source region disposed underneath the corners immediately next to the trenches having a lower net concentration of impurities of the first conductivity type than remaining portion of the source region.

Abstract translation: 本发明包括具有第一导电类型的衬底，其顶表面包括设置在其中的至少两个相交的沟槽，其中衬有沟槽的绝缘层和填充沟槽的导电材料。 晶体管还包括第一导电类型的源极区域，从邻近沟槽的衬底的顶表面朝向衬底延伸。 晶体管还具有与第一导电类型相反极性的第二导电类型的主体区域，主体区域从与沟槽相邻的顶表面延伸到衬底并围绕源极区域。 填充沟槽的导电材料包括覆盖由相交沟槽限定的电池角部的穿通抑制块，其中设置在紧邻沟槽的角下方的源极区域具有比剩余部分更低的第一导电类型的杂质的净浓度 的源地区。

公开(公告)号：US5907169A

公开(公告)日：1999-05-25

申请号：US844165

申请日：1997-04-18

Applicant: Fwu-Iuan Hshieh ,  True-Lon Lin ,  Koon Chong So

Inventor： Fwu-Iuan Hshieh ,  True-Lon Lin ,  Koon Chong So

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76

CPC classification number: H01L29/7813 ,  H01L21/28114 ,  H01L21/2815 ,  H01L29/402 ,  H01L29/0638 ,  H01L29/0847 ,  H01L29/4232 ,  H01L29/4238

Abstract: The present invention discloses a MOSFET transistor supported on a substrate. The MOSFET transistor includes an epitaxial-layer of a first conductivity type near a top surface of the substrate defining a drain region therein. The MOSFET transistor further includes an oxide block supported on a raised silicon terrace of the epitaxial layer disposed in a central portion of the transistor above a JFET reduction region of a first conductivity type of higher dopant concentration than the epitaxial layer. The MOSFET transistor further includes a lower-outer body region of a second conductivity type surrounding the JFET reduction region disposed near the top surface and defining a boundary of the MOSFET transistor. The MOSFET transistor further includes a source region of the first conductivity type enclosed in the lower-outer body region disposed near the top surface and extended to the transistor boundary. The MOSFET transistor further includes a thin gate oxide layer overlying the top surface of the substrate and an edge of the raised oxide terrace. The MOSFET transistor further includes a polysilicon gate overlaying the oxide block and the silicon terrace, the gate further covering an area above the source region and the body region insulated by the gate oxide layer therefrom.

Abstract translation: 本发明公开了一种支撑在基板上的MOSFET晶体管。 MOSFET晶体管包括在衬底的顶表面附近限定其中的漏极区的第一导电类型的外延层。 MOSFET晶体管还包括负载在外延层的凸起的硅平台上的氧化物块，该外延层设置在晶体管的中心部分的第一导电类型比外延层高的掺杂剂浓度的JFET还原区之上。 MOSFET晶体管还包括围绕设置在顶表面附近并限定MOSFET晶体管的边界的JFET还原区的第二导电类型的下外体体区域。 MOSFET晶体管还包括封装在设置在顶表面附近并延伸到晶体管边界的下外体体区中的第一导电类型的源极区域。 MOSFET晶体管还包括覆盖在衬底的顶表面上的薄栅极氧化物层和凸起的氧化物露台的边缘。 所述MOSFET晶体管还包括覆盖所述氧化物块和所述硅平台的多晶硅栅极，所述栅极还覆盖所述源极区域上方的区域以及由所述栅极氧化物层绝缘的所述主体区域。

公开(公告)号：US5729037A

公开(公告)日：1998-03-17

申请号：US638639

申请日：1996-04-26

Applicant: Fwu-Iuan Hshieh ,  Yan Man Tsui ,  True-Lon Lin ,  Danny Chi Nim ,  Koon Chong So

Inventor： Fwu-Iuan Hshieh ,  Yan Man Tsui ,  True-Lon Lin ,  Danny Chi Nim ,  Koon Chong So

IPC: H01L21/336 ,  H01L29/36 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L29/66712 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/7811 ,  H01L29/36

Abstract: Improved power MOSFET structure, and fabrication process are disclosed in this invention to achieve a low threshold voltage. The improved MOSFET device is formed in a semiconductor substrate with a drain region formed near a bottom surface of the substrate supporting a plurality of double-diffused vertical cells thereon wherein each of the vertical cells including a pn-junction having a body region surrounding a source region and each of the vertical cell further including a gate above the pn-junction. Each of the vertical cells further includes a source-dopant segregation reduction layer for reducing a surface segregation between the source region and an oxide layer underneath the gate whereby the body surface peak dopant concentration near an interface between the source region and the body region is reduced for reducing a threshold voltage of the MOSFET device. In another preferred embodiment, the source-dopant segregation reduction layer includes a LPCVD nitride layer formed on top of the polysilicon gates.

Abstract translation: 在本发明中公开了改进的功率MOSFET结构和制造工艺以实现低阈值电压。 改进的MOSFET器件形成在半导体衬底中，其中在衬底的底表面附近形成有漏极区域，该漏极区域支撑多个双扩散垂直电池，其中每个垂直单元包括具有围绕源极的体区的pn结 区域，并且每个垂直单元还包括在pn结上方的栅极。 每个垂直单元还包括用于减少源极区域和栅极之下的氧化物层之间的表面偏析的源极 - 掺杂剂偏析还原层，从而源极区域和体区域之间的界面附近的体表面峰值掺杂剂浓度降低 用于降低MOSFET器件的阈值电压。 在另一个优选的实施方案中，源 - 掺杂剂分离还原层包括形成在多晶硅栅极顶部的LPCVD氮化物层。

公开(公告)号：US5648297A

公开(公告)日：1997-07-15

申请号：US646795

申请日：1996-05-21

Applicant: True-Lon Lin ,  Jin S. Park ,  Sarath D. Gunapala ,  Eric W. Jones ,  Hector M. Del Castillo

Inventor： True-Lon Lin ,  Jin S. Park ,  Sarath D. Gunapala ,  Eric W. Jones ,  Hector M. Del Castillo

IPC: H01L29/36 ,  H01L31/108 ,  H01L31/00 ,  H01L21/44

CPC classification number: H01L31/108 ,  H01L29/365 ,  Y10S977/759

Abstract: Extended cutoff wavelengths of PtSi Schottky infrared detectors in the long wavelength infrared (LWIR) regime have been demonstrated for the first time. This result was achieved by incorporating a 1-nm-thick p+ doping spike at the PtSi/Si interface. The extended cutoff wavelengths resulted from the combined effects of an increased electric field near the silicide/Si interface due to the p+ doping spike and the Schottky image force. The p+ doping spikes were grown by molecular beam epitaxy at 450 degrees Celsius using elemental boron as the dopant source, with doping concentrations ranging from 1.times.10.sup.19 to 1.times.10.sup.21 cm.sup.-3. The cutoff wavelengths were shown to increase with increasing doping concentrations of the p+ spikes.

Abstract translation: 长波长红外（LWIR）方式的PtSi肖特基红外探测器的延长截止波长已经首次被证明。 该结果通过在PtSi / Si界面上并入1nm厚的p +掺杂尖峰来实现。 由于p +掺杂尖峰和肖特基图像力，由于硅化物/ Si界面附近的增加的电场的组合效应导致延伸的截止波长。 使用元素硼作为掺杂剂源，在450摄氏度下通过分子束外延生长p +掺杂尖峰，掺杂浓度范围为1×10 19至1×10 21 cm -3。 截止波长显示随着p +峰值掺杂浓度的增加而增加。

公开(公告)号：US5075243A

公开(公告)日：1991-12-24

申请号：US677373

申请日：1991-03-27

Applicant: Kai-Wei Nieh ,  True-Lon Lin ,  Robert W. Fathauer

Inventor： Kai-Wei Nieh ,  True-Lon Lin ,  Robert W. Fathauer

IPC: G03F7/004 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285

CPC classification number: G03F7/0042 ,  H01L21/0332 ,  H01L21/28097 ,  H01L21/28518 ,  Y10S148/046 ,  Y10S148/048 ,  Y10S148/154

Abstract: Amorphous Co:Si (1:2 ratio) films (12) are electron gun-evaporated on clean Si(111) substrates (10), such as in a molecular beam epitaxy system. These layers are then crystallized selectively with a focused electron beam (14) to form very small crystalline CoSi.sub.2 regions (12') in an amorphous matrix. Finally, the amorphous regions are etched away selectively using plasma or chemical techniques.

Abstract translation: 非晶Co：Si（1:2比）膜（12）在清洁的Si（111）衬底（10）上电子枪蒸发，例如在分子束外延系统中。 然后用聚焦电子束（14）选择性地结晶这些层，以在无定形基质中形成非常小的晶体CoSi 2区域（12'）。 最后，使用等离子体或化学技术选择性地蚀刻非晶区域。

公开(公告)号：US4990988A

公开(公告)日：1991-02-05

申请号：US363815

申请日：1989-06-09

Applicant: True-Lon Lin

Inventor： True-Lon Lin

IPC: H01L27/148 ,  H01L31/028 ,  H01L31/108

CPC classification number: H01L31/0284 ,  H01L27/14881 ,  H01L31/108

Abstract: Laterally stacked Schottky diodes (25) for infrared sensor applications are fabricated utilizing porous silicon (10) having pores (12). A Schottky metal contact (24) is formed in the pores, such as by electroplating. The sensors may be integrated with silicon circuits on the same chip with a high quantum efficiency, which is ideal for IR focal plane array applications due to uniformity and reproducibility.

Abstract translation: 使用具有孔（12）的多孔硅（10）制造用于红外传感器应用的横向堆叠的肖特基二极管（25）。 在孔中形成肖特基金属接触（24），例如通过电镀。 传感器可以与同一芯片上的硅电路集成，具有高量子效率，由于均匀性和重现性，这对于红外焦平面阵列应用是理想的。