利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

18 条记录 (耗时 0.018 秒)

    Dedicated input/output first in/first out module for a field programmable gate array
    1.
    发明申请
    Dedicated input/output first in/first out module for a field programmable gate array 失效

    公开(公告)号：US20060087341A1

    公开(公告)日：2006-04-27

    申请号：US11295889

    申请日：2005-12-06

    申请人： William Plants ,  Arunangshu Kundu

    发明人： William Plants ,  Arunangshu Kundu

    IPC分类号： H03K19/177

    CPC分类号： H03K19/1776 ,  H03K19/17744

    摘要： A field programmable gate array architecture having a plurality of input/output pads comprising: a plurality of logic clusters; a plurality of input/output clusters; a plurality of input/output buffers; a plurality of dedicated input/output first-in/first-out memory blocks, the dedicated input/output first-in/first-out memory blocks having a first-in/first-out memory coupled to one of the plurality of input/output pads; and a routing interconnect architecture programmably coupling the logic clusters, input/output buffers and the input/output clusters, wherein the dedicated input/output first-in/first-out memory blocks are programmably coupled between the input/output buffers and the input/output clusters.

    Field programmable gate array and microcontroller system-on-a-chip
    2.
    发明申请
    Field programmable gate array and microcontroller system-on-a-chip 有权
    现场可编程门阵列和微控制器片上系统

    公开(公告)号：US20050257031A1

    公开(公告)日：2005-11-17

    申请号：US11187068

    申请日：2005-07-22

    申请人： Arunangshu Kundu ,  Arnold Goldfein ,  William Plants ,  David Hightower

    发明人： Arunangshu Kundu ,  Arnold Goldfein ,  William Plants ,  David Hightower

    IPC分类号： G06F9/00 ,  G06F15/78 ,  H01L21/82 ,  H03K19/173

    CPC分类号： G06F15/7842 ,  G06F15/7867

    摘要： A system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherein the inputs are connected to the field programmable gate array core, a microcontroller, a microcontroller virtual component interface translator having input and outputs, wherein the inputs are connected to the microcontroller, a system bus connected to the outputs of the field programmable gate array virtual component interface translator and also to the outputs of said microcontroller virtual component interface translator, and direct connections between the microcontroller and the routing resources of the field programmable gate array core.

    摘要翻译： 片上系统集成电路具有具有逻辑集群，静态随机存取存储器模块和路由资源的现场可编程门阵列核心，具有输入和输出的现场可编程门阵列虚拟组件接口转换器，其中输入被连接 到现场可编程门阵列核心，微控制器，具有输入和输出的微控制器虚拟组件接口转换器，其中输入连接到微控制器，连接到现场可编程门阵列虚拟组件接口转换器的输出的系统总线，以及 到所述微控制器虚拟组件接口转换器的输出，以及微控制器与现场可编程门阵列核心的路由资源之间的直接连接。

    Multi-level routing architecture in a field programmable gate array having transmitters and receivers
    3.
    发明申请
    Multi-level routing architecture in a field programmable gate array having transmitters and receivers 失效
    具有发射机和接收机的现场可编程门阵列中的多级路由架构

    公开(公告)号：US20050146354A1

    公开(公告)日：2005-07-07

    申请号：US11074922

    申请日：2005-03-07

    申请人： Arunangshu Kundu ,  Venkatesh Narayanan ,  John McCollum ,  William Plants

    发明人： Arunangshu Kundu ,  Venkatesh Narayanan ,  John McCollum ,  William Plants

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17736

    摘要： A routing architecture in a field programmable gate array (FPGA) having a plurality of logic clusters wherein each logic cluster has at least two sub-clusters. The logic clusters are arranged in rows and columns and each logic clusters has a plurality of receiver components, a plurality of transmitter components, at least one buffer module, at least one sequential logic component and at least one combinatorial logic component. A first-level routing architecture is programmably coupled to the logic clusters and a second-level routing architecture is programmably coupled to the logic clusters and to the first-level routing architecture through at least one of the transmitter components and at least one of the receiver components.

    摘要翻译： 具有多个逻辑集群的现场可编程门阵列（FPGA）中的路由架构，其中每个逻辑集群具有至少两个子集群。 逻辑簇以行和列排列，并且每个逻辑簇具有多个接收器组件，多个发射器组件，至少一个缓冲器模块，至少一个顺序逻辑组件和至少一个组合逻辑组件。 第一级路由架构可编程地耦合到逻辑集群，并且第二级路由架构可编程地耦合到逻辑集群，并通过至少一个发送器部件和至少一个接收器耦合到第一级路由架构 组件。

    Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array
    4.
    发明申请
    Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array 失效
    辐射硬化静态随机存取存储器现场可编程门阵列中误差检测和校正的装置和方法

    公开(公告)号：US20060145722A1

    公开(公告)日：2006-07-06

    申请号：US11367081

    申请日：2006-03-02

    申请人： William Plants

    发明人： William Plants

    IPC分类号： H03K19/007

    CPC分类号： G06F11/1008 ,  G11C5/005 ,  G11C11/4125 ,  H01L27/118 ,  H03K19/00338 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/1778

    摘要： The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the routing resources. Error correction circuitry coupled to the configuration data lines analyzes and corrects any errors in the configuration data that may occur due to a single event upset (SEU).

    摘要翻译： 本系统包括具有将逻辑模块耦合在一起的逻辑模块和路由资源的辐射容忍可编程逻辑器件。 提供配置数据的配置数据线控制逻辑模块和路由资源的编程。 耦合到配置数据线的错误校正电路分析和校正由于单个事件不正常（SEU）而可能发生的配置数据中的任何错误。

    SRAM BUS ARCHITECTURE AND INTERCONNECT TO AN FPGA
    5.
    发明申请
    SRAM BUS ARCHITECTURE AND INTERCONNECT TO AN FPGA 失效
    SRAM总线架构和与FPGA的连接

    公开(公告)号：US20070182600A1

    公开(公告)日：2007-08-09

    申请号：US11688688

    申请日：2007-03-20

    申请人： William Plants

    发明人： William Plants

    IPC分类号： H03M7/38

    CPC分类号： G11C7/10 ,  G11C7/18 ,  G11C8/10 ,  H03K19/17736 ,  H03K19/1776

    摘要： An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connected in parallel with a tri-state buffer. The pass transistors and tri-state buffers are controlled by configuration SRAM bits. Some of the pass-through interconnect conductors are connected by programmable elements to the address, data and control signal lines of the SRAM blocks, while other pass through the SRAM blocks with out being further connected to the SRAM bussing architecture.

    摘要翻译： SRAM总线架构包括直通互连导体。 每个直通互连导体通过包括与三态缓冲器并联连接的传输晶体管的元件连接到FPGA的通用互连架构的路由通道。 传输晶体管和三态缓冲器由配置SRAM位控制。 一些直通互连导体通过可编程元件连接到SRAM块的地址，数据和控制信号线，而其他通过SRAM块进一步连接到SRAM总线架构。

    SRAM bus architecture and interconnect to an FPGA
    6.
    发明申请
    SRAM bus architecture and interconnect to an FPGA 失效

    公开(公告)号：US20060193181A1

    公开(公告)日：2006-08-31

    申请号：US11410415

    申请日：2006-04-24

    申请人： William Plants

    发明人： William Plants

    IPC分类号： G11C5/00 ,  G11C7/10

    CPC分类号： G11C7/10 ,  G11C7/18 ,  G11C8/10 ,  H03K19/17736 ,  H03K19/1776

    摘要： An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connected in parallel with a tri-state buffer. The pass transistors and tri-state buffers are controlled by configuration SRAM bits. Some of the pass-through interconnect conductors are connected by programmable elements to the address, data and control signal lines of the SRAM blocks, while other pass through the SRAM blocks with out being further connected to the SRAM bussing architecture.

    Flash-based FPGA with secure reprogramming
    8.
    发明授权
    Flash-based FPGA with secure reprogramming 有权
    基于闪存的FPGA，具有安全的重新编程

    公开(公告)号：US07616508B1

    公开(公告)日：2009-11-10

    申请号：US11463846

    申请日：2006-08-10

    申请人： Joel Landry ,  William Plants ,  Randall Sexton

    发明人： Joel Landry ,  William Plants ,  Randall Sexton

    IPC分类号： G11C7/00 ,  G06F17/50

    CPC分类号： H03K19/17748 ,  G11C16/102 ,  H03K19/17732 ,  H03K19/17768

    摘要： A flash-based programmable integrated circuit includes programmable circuitry, a flash memory array coupled to the programmable circuitry for configuring it, flash programming circuitry for programming the flash memory array, and an on-chip intelligence, such as a microcontroller or state machine, coupled to the programming circuitry to program the flash memory from off-chip data supplied via an I/O pad, or to refresh the data stored in the flash memory to prevent it from degrading.

    摘要翻译： 基于闪存的可编程集成电路包括可编程电路，耦合到可编程电路的闪存阵列，用于配置它，用于对闪速存储器阵列进行编程的闪存编程电路，以及诸如微控制器或状态机的片上智能，耦合 编程电路通过I / O焊盘提供的片外数据对闪速存储器进行编程，或刷新存储在闪速存储器中的数据，以防止其降级。

    Deglitching circuits for a radiation-hardened static random access memory based programmable architecture
    10.
    发明申请
    Deglitching circuits for a radiation-hardened static random access memory based programmable architecture 有权

    公开(公告)号：US20060126376A1

    公开(公告)日：2006-06-15

    申请号：US11323417

    申请日：2005-12-30

    申请人： William Plants

    发明人： William Plants

    IPC分类号： G11C11/41 ,  G11C11/00

    CPC分类号： G11C11/4125

    摘要： The present invention comprises a device and a method for a deglitching circuit for a radiation tolerant static random access memory (SRAM) based field programmable gate array. The deglitching circuit for a radiation tolerant static random access memory (SRAM) based field programmable gate array comprises a configuration memory that has a plurality of configuration bits Read and write circuitry is provided to configure the plurality of configuration bits. A radiation hard latch is coupled to and controls a programmable element and an interface couples at least one of the plurality of configuration bits to the radiation hard latch when the write circuitry writes to the plurality of configuration bits.