-
公开(公告)号：US20170373671A1
公开(公告)日：2017-12-28
申请号：US15628668
申请日：2017-06-21
申请人： WILLIAM REDMAN-WHITE
发明人： WILLIAM REDMAN-WHITE
CPC分类号： H03J5/244 , G06K7/10148 , H02J7/025 , H02J50/12 , H03J1/06 , H03J5/24 , H03J2200/06 , H03J2200/10 , H04B5/0031 , H04B5/0037 , H04B5/0075
摘要： A system is described for maintaining an inductive-capacitive (LC) network at resonance while the excitation frequency may be varied between a number of discrete frequencies at desired instants controlled by a modulation input, while taking into account component parameter errors due environmental and ageing as well as manufacturing tolerances. Control of the resonance while the excitation frequency changes permits the transmission of frequency modulation (FM) or frequency shift keying (FSK) information through an inductively coupled power transfer system.
-
公开(公告)号：US08283955B2
公开(公告)日：2012-10-09
申请号：US12916452
申请日：2010-10-29
申请人： William Redman-White
发明人： William Redman-White
IPC分类号： H03L7/06
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/222 , G11C11/4076 , G11C2207/2254
摘要： The present invention relates to a double data rate interface and method for use between a processor and random access memory, comprising a delay line including means for creating a delay in a data strobe signal from the random access memory, the delay line being arranged such that the delay in the data strobe signal is equal to the sum of set-up time and data bus rise time. The interface of includes the delay line comprising the delay locked loop which in turn comprises a ring oscillator. The ring oscillator includes a buffer and a Vernier delay.
摘要翻译： 本发明涉及在处理器与随机存取存储器之间使用的双数据速率接口和方法，包括延迟线，包括用于从随机存取存储器产生数据选通信号的延迟的装置，所述延迟线被布置成使得 数据选通信号的延迟等于设置时间和数据总线上升时间之和。 该接口包括延迟线，延迟线包括延迟锁定环，该延迟锁定环又包括环形振荡器。 环形振荡器包括缓冲器和游标延迟。
-
公开(公告)号：US07536165B2
公开(公告)日：2009-05-19
申请号：US10202035
申请日：2002-07-24
申请人： William Redman-White
发明人： William Redman-White
IPC分类号： H04B1/24
CPC分类号： H03D7/1425 , H03B2201/0208 , H03D7/1433 , H03D7/1458 , H03D2200/0043 , H03D2200/0047 , H03D2200/009 , H03K17/14 , H03K17/603 , H03K17/6264
摘要： A direct conversion receiver includes a detector that provides a measure of bias offset that is caused by component mismatches in the direct conversion mixer, and a corrective network that reduces the bias offset based on this measure. The direct conversion mixer demodulates a radio-frequency (RF) input signal via mixing with a local-oscillator (LO) signal to provide a differential baseband output signal. A differential peak detector compares the peak signal value at each side of the mixer's differential output, and a differential integrator averages the difference between these peak signal values to provide the measure of bias offset. The corrective network adds a correction offset to each of the local oscillator local oscillator paths on each of the switching pairs that provide the differential output, but opposite to the local oscillator connections. By applying the correction offset to the opposing transistor in each pair, the difference in switching time between the pairs is reduced, and, correspondingly, the differential-mode leakage from the local oscillator to the RF input stage is reduced.
摘要翻译： 直接转换接收机包括检测器，该检测器提供由直接转换混频器中的部件不匹配引起的偏移偏移的度量，以及基于该测量减少偏移偏移的校正网络。 直接转换混频器通过与本地振荡器（LO）信号混频解调射频（RF）输入信号，以提供差分基带输出信号。 差分峰值检测器比较混频器差分输出的每一侧的峰值信号值，差分积分器对这些峰值信号值之间的差异进行平均，以提供偏置偏移的测量。 校正网络为提供差分输出但与本地振荡器连接相反的每个开关对上的每个本地振荡器本地振荡器路径增加了校正偏移。 通过将校正偏移应用于每对中的对置晶体管，减小了对之间的切换时间差，相应地减小了从本地振荡器到RF输入级的差模泄漏。
-
公开(公告)号：US06784741B1
公开(公告)日：2004-08-31
申请号：US09712677
申请日：2000-11-14
申请人： William Redman-White
发明人： William Redman-White
IPC分类号： H03G312
CPC分类号： H03G1/0023 , H03F3/45103 , H03F2200/294 , H03F2200/372 , H03F2203/45311 , H03F2203/45364 , H03F2203/45386 , H03F2203/45396 , H03F2203/45506
摘要： A low noise amplifier with switchable gain settings comprises a cascoded emitter coupled pair (T1, T2, T5, T6; T3, T4, T7, T8) having a current diverter (T9, T10) which reduces the gain to an intermediate level in response to a control signal on terminals (8, 9). Further control signals on terminals (5, 10, 11, 12, 13) reduce the gain to a low level by introducing emitter degeneration (R3). To compensate for the increase in input impedance caused by the introduction of emitter degeneration feedback loops (C1, R8; C2, R9) are connected between the diversion path and the amplifier inputs.
摘要翻译： 具有可切换增益设置的低噪声放大器包括具有电流分流器（T9，T10）的级联发射极耦合对（T1，T2，T5，T6; T3，T4，T7，T8），其将增益降低到响应中间级 到端子（8,9）上的控制信号。 通过引入发射极退化（R3），端子（5,10,11,12,13）上的进一步的控制信号将增益降低到低电平。 为了补偿由引入发射极退化反馈回路（C1，R8; C2，R9）引起的输入阻抗的增加连接在引导路径和放大器输入之间。
-
公开(公告)号：US6104330A
公开(公告)日：2000-08-15
申请号：US83697
申请日：1998-05-21
申请人： William Redman-White , Mark Bracey
发明人： William Redman-White , Mark Bracey
CPC分类号： H03M1/0678 , H03M1/742
摘要： A digital to anologue converter comprises a plurality of current sources (T.sub.o -T.sub.n) and corresponding selection switches (D.sub.o -D.sub.n) which connect the current sources to an output (3). In order to enable a constant capacitance to be presented at the output (3) regardless of the input digital code a plurality of dummy current sources (T.sub.o -T.sub.n) which take the same form as the current sources (To-T.sub.n) are provided. The dummy current sources have associated selection switches ( D.sub.o -D.sub.n) which are operated by the logical inverse of the code applied to the current sources (T.sub.o -T.sub.n).
摘要翻译： 数字到厌恶变换器包括将电流源连接到输出（3）的多个电流源（To-Tn）和相应的选择开关（Do-Dn）。 为了能够在输出（3）上呈现恒定电容，无论输入数字代码如何，多个虚拟电流源（+ E，ovs T + EE o- + E，ovs T + EE n） 提供与当前来源（To-Tn）相同的形式。 虚拟电流源具有由应用于当前源（To-Tn）的代码的逻辑反相操作的相关选择开关（+ E，ov D + EE o- + E，ov D + EE n）。
-
公开(公告)号：US5714894A
公开(公告)日：1998-02-03
申请号：US567255
申请日：1995-12-05
申请人： William Redman-White , Mark Bracey
发明人： William Redman-White , Mark Bracey
IPC分类号： G01R19/165 , G11C27/02 , H03K5/08
CPC分类号： G11C27/028
摘要： A current comparator arrangement has first and second inputs (100, 103), an output (105), and cross-coupled transistors (MP1, MP2) which form a latching circuit. The arrangement also includes current stores (MP3, MP4), the input currents to be compared being fed to the current stores in a selected forward differential order for storage therein during a first portion of a clock period in which the cross-coupled latching circuit is reset. During a second portion of the clock period the input current connections are reversed, thereby reversing their differential order, and the reverse order currents are supplied together with the stored forward order currents to the latching circuit. This cancels common mode and offset currents so that they do not affect the comparison of the input currents.
摘要翻译： 电流比较器装置具有形成锁存电路的第一和第二输入（100,103），输出（105）和交叉耦合晶体管（MP1，MP2）。 该布置还包括当前存储（MP3，MP4），要被比较的输入电流以所选择的前向差分顺序馈送到当前存储器，以在其中交叉耦合锁存电路是交叉耦合锁存电路的时钟周期的第一部分期间存储 重启。 在时钟周期的第二部分期间，输入电流连接被反转，从而反转它们的差分顺序，并且逆向电流与存储的正向电流一起提供给锁存电路。 这取消了共模和偏移电流，使其不影响输入电流的比较。
-
公开(公告)号：US06963625B2
公开(公告)日：2005-11-08
申请号：US09918834
申请日：2001-08-01
CPC分类号： H03M13/3961 , G06G7/14 , H03M13/4107
摘要： An arrangement for selecting the largest of a plurality of input currents (pma (k−1), pmb (k−1)) and adding a further current (Ibmk) to the selected current, the arrangement comprising: a plurality of inputs (901, 902) for receiving said input currents; a further input (905) for receiving said further current; an output (906, 907) for delivering an output current proportional to the sum of the largest of the input currents and the further current; means for feeding each of the received input currents to the main current conducting path of a respective transistor, (T900, T902) each of the transistors having its control electrode connected to a common point; a respective follower transistor (T901, T903) connected between the input and the common point; and a mirror transistor (T904) having its control electrode connected to the common point for producing a current whose value is related to that of the largest input current.The currents through transistors (T904, T907) are summed and sensed by a diode connected transistor (T905) whose gate voltage is stored on a capacitor (C900, C901) by means of respective switches (S900, S901). The voltages across the capacitors (C900, C901) are fed via respective switches (S902, S903) to the gate electrodes of transistors (T908, T909) whose drain electrodes feed an output current (pmc (k−1)) to outputs (906, 907) of the arrangement.A plurality of such arrangements are used for producing path metric currents for a Viterbi decoder.
摘要翻译： 一种用于选择多个输入电流中最大的输入电流（pma（k-1），pmb（k-1））并将另外的电流（Ibmk）加到所选择的电流的装置，该装置包括：多个输入端 ，902），用于接收所述输入电流; 用于接收所述另外的电流的另外的输入（905）; 输出（906,907），用于传送与最大输入电流和另外的电流的和成比例的输出电流; 用于将每个所接收的输入电流馈送到相应晶体管的主电流传导路径（T 900，T 902）的装置，每个晶体管的控制电极连接到公共点; 连接在输入和公共点之间的相应跟随器晶体管（T 901，T 903） 以及其控制电极连接到公共点的反射镜晶体管（T 904），用于产生其值与最大输入电流的电流相关的电流。 通过晶体管（T 904，T 907）的电流由其栅极电压通过相应的开关存储在电容器（C 900，C 901）上的二极管连接的晶体管（T 905）被相加和感测（S 900，S 901 ）。 电容器（C 900，C 901）上的电压通过各自的开关（S 902，S 903）馈送到晶体管（T 908，T 909）的栅电极，其漏电极馈送输出电流（pmc（k-1 ））到该装置的输出（906,907）。 多个这样的布置用于产生用于维特比解码器的路径度量电流。
-
公开(公告)号：US06542103B2
公开(公告)日：2003-04-01
申请号：US09920037
申请日：2001-08-01
IPC分类号： H03M134
CPC分类号： H03M13/4169 , G11B20/10009
摘要： An arrangement for generating an error signal representing the differences between an input signal voltage level (xpk, xnk) and an estimated value (rp, rn) for the input signal voltage level comprises first (T1, T2) and second (T5, T6) transconductors and a differencing circuit (T3, T4, T7, T8) which forms the modulus of the difference between the outputs of the transconductors. The error signal is converted into a probability signal by subtracting the error signal from a constant signal (408) to produce a signal at the output (407) which is a maximum when the input voltage level and estimated voltage level are equal.
摘要翻译： 用于产生表示输入信号电压电平（xpk，xnk）与输入信号电压电平的估计值（rp，rn）之间的差的误差信号的装置包括第一（T1，T2）和第二（T5，T6） 跨导体和差分电路（T3，T4，T7，T8），其形成跨导体的输出之间的差的模数。 通过从恒定信号（408）中减去误差信号来将误差信号转换成概率信号，以在输入（407）产生信号，当输入电压电平和估计电压电平相等时，该信号为最大值。
-
9.发明授权
公开(公告)号：US5745007A
公开(公告)日：1998-04-28
申请号：US691775
申请日：1996-08-02
申请人： William Redman-White
发明人： William Redman-White
CPC分类号： H03F3/45708 , H03F3/45237 , H03F2203/45371 , H03F2203/45408
摘要： An amplifier, particularly a CMOS amplifier has a differential input which is fed to six differential pairs. The outputs of the first and third differential pair are combined and fed to inputs of a summing network, while the outputs of the fourth and fifth are combined and fed to inputs of the summing network. The second and sixth differential pairs are arranged to cancel the tail currents of the fifth and third pairs, respectively, when all of the devices are in their active state. Thus, regardless of the common mode input level with respect to the supply rails the output current is provided by four devices giving a constant g.sub.m and slew rate.
摘要翻译： 放大器，特别是CMOS放大器具有馈送到六个差分对的差分输入。 第一和第三差分对的输出被组合并馈送到求和网络的输入，而第四和第五差分对的输出被组合并馈送到求和网络的输入。 第二和第六差分对被配置为当所有装置处于其活动状态时分别消除第五和第三对的尾部电流。 因此，无论相对于电源轨的共模输入电平如何，输出电流由四个器件提供，给定恒定的gm和转换速率。
-
公开(公告)号：US10171131B2
公开(公告)日：2019-01-01
申请号：US15328398
申请日：2015-10-16
申请人： William Redman-White
发明人： William Redman-White
摘要： A system is provided that can automatically adjust a tuned circuit to resonate at the frequency of an applied excitation signal. The error in the resonant frequency of the tuned circuit is determined in real time from signals derived from within the network. The system permits the use of a time varying excitation frequency in a high Q circuit, including modulation conveying information. The tuning information may be stored in a memory and used to set the tuning instantaneously in order to maintain resonance when the excitation frequency changes abruptly, for example when frequency shift keying is used.
-
-
-
-
-
-
-
-
-
搜索结果
29 条记录 (耗时 0.017 秒)
