公开(公告)号：US20080285375A1

公开(公告)日：2008-11-20

申请号：US12124765

申请日：2008-05-21

申请人： Yasurou Matsuzaki

发明人： Yasurou Matsuzaki

IPC分类号： G11C8/18 ,  H03L7/00

CPC分类号： G11C7/1057 ,  G06F1/10 ,  G06F5/06 ,  G11C5/063 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222 ,  H03L7/07 ,  H03L7/081

摘要： A module includes a semiconductor device, a phase adjustment circuit generating a second clock so that a phase adjustment signal output from the semiconductor device and a first clock have a predetermined phase relationship, and an output circuit that is provided in the semiconductor device and generates the phase adjustment signal from the second clock.

摘要翻译： 模块包括半导体器件，产生第二时钟的相位调整电路，使得从半导体器件输出的相位调整信号和第一时钟具有预定的相位关系，以及设置在半导体器件中的输出电路， 来自第二个时钟的相位调整信号。

公开(公告)号：US07345942B2

公开(公告)日：2008-03-18

申请号：US11413204

申请日：2006-04-28

申请人： Yasurou Matsuzaki

发明人： Yasurou Matsuzaki

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/4072 ,  G11C11/4094 ,  G11C2211/4061 ,  G11C2211/4065

摘要： According to the present invention, a memory circuit requiring refresh operations a first circuit which receives a command in synchronization with a clock signal, and which generates a first internal command internally and a second circuit which generates a second internal command, e.g., a refresh command, internally in a prescribed refresh cycle. And an internal circuit, according to said first internal command, executes corresponding control through clock-synchronous operations, and when said refresh command is issued, sequentially executes control corresponding to the refresh command and control corresponding to said first internal command through clock-asynchronous operations. According to the present invention, when a refresh timing signal is generated, the refresh operation can be intrupted among the external command operations.

摘要翻译： 根据本发明，一种需要刷新操作的存储电路，第一电路接收与时钟信号同步的命令，并且内部产生第一内部命令，第二电路产生第二内部命令，例如刷新命令 在规定的刷新周期内部。 并且根据所述第一内部命令，内部电路通过时钟同步操作执行相应的控制，并且当发出所述刷新命令时，通过时钟异步操作顺序执行对应于刷新命令的控制和对应于所述第一内部命令的控制 。 根据本发明，当产生刷新定时信号时，可以在外部命令操作中中断刷新操作。

公开(公告)号：US20070206431A1

公开(公告)日：2007-09-06

申请号：US11790834

申请日：2007-04-27

申请人： Yasurou Matsuzaki

发明人： Yasurou Matsuzaki

IPC分类号： G11C11/4072

CPC分类号： G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/4072 ,  G11C11/4094 ,  G11C2211/4061 ,  G11C2211/4065

摘要： According to the present invention, a memory circuit requiring refresh operations a first circuit which receives a command in synchronization with a clock signal, and which generates a first internal command internally and a second circuit which generates a second internal command, e.g., a refresh command, internally in a prescribed refresh cycle. And an internal circuit, according to said first internal command, executes corresponding control through clock-synchronous operations, and when said refresh command is issued, sequentially executes control corresponding to the refresh command and control corresponding to said first internal command through clock-asynchronous operations. According to the present invention, when a refresh timing signal is generated, the refresh operation can be interrupted among the external command operations.

摘要翻译： 根据本发明，一种需要刷新操作的存储电路，第一电路接收与时钟信号同步的命令，并且内部产生第一内部命令，第二电路产生第二内部命令，例如刷新命令 在规定的刷新周期内部。 并且根据所述第一内部命令，内部电路通过时钟同步操作执行相应的控制，并且当发出所述刷新命令时，通过时钟异步操作顺序执行对应于刷新命令的控制和对应于所述第一内部命令的控制 。 根据本发明，当产生刷新定时信号时，可以在外部命令操作之间中断刷新操作。

公开(公告)号：US07154799B2

公开(公告)日：2006-12-26

申请号：US11098557

申请日：2005-04-05

申请人： Yasurou Matsuzaki

发明人： Yasurou Matsuzaki

IPC分类号： G11C7/00

CPC分类号： G11C7/1045 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622 ,  G11C2211/4067

摘要： Flags are formed to respectively correspond to memory cell groups each including volatile memory cells. Each flag indicates as a set state that the memory cells store data in a second memory mode. In a changing operation of changing from a first memory mode in which data is independently retained by each memory cell to a second memory mode in which same data are retained in the memory cells of each memory cell group, each flag is reset in response to the first access to the corresponding memory cell group. Therefore, only the first access is made in the second memory mode in each memory cell group. The memory cells are accessed in a mode according to the flag in the changing operation, thereby allowing a system managing the semiconductor memory to freely access the memory cells even during the changing operation. Consequently, a practical changing time can be eliminated.

摘要翻译： 标志分别形成为分别对应于包括易失性存储单元的存储单元组。 每个标志指示存储器单元将数据存储在第二存储器模式中的设置状态。 在从每个存储器单元独立地保持数据的第一存储器模式改变为在每个存储单元组的存储单元中保留相同数据的第二存储器模式的改变操作中，每个标志响应于 首先访问相应的存储单元组。 因此，在每个存储单元组中仅在第二存储器模式中进行第一次访问。 存储单元按照改变操作中的标志在模式下访问，从而即使在改变操作期间也允许管理半导体存储器的系统自由地访问存储单元。 因此，可以消除实际的改变时间。

公开(公告)号：US07120761B2

公开(公告)日：2006-10-10

申请号：US10284092

申请日：2002-10-31

申请人： Yasurou Matsuzaki ,  Takaaki Suzuki ,  Masafumi Yamazaki ,  Kenichi Kawasaki ,  Shinnosuke Kamata ,  Ayako Sato ,  Masato Matsumiya

发明人： Yasurou Matsuzaki ,  Takaaki Suzuki ,  Masafumi Yamazaki ,  Kenichi Kawasaki ,  Shinnosuke Kamata ,  Ayako Sato ,  Masato Matsumiya

IPC分类号： G06F12/00

CPC分类号： G11C8/16 ,  G06F13/1605 ,  G11C7/1039 ,  G11C7/1075 ,  G11C7/1078 ,  G11C7/22 ,  G11C8/18 ,  G11C11/24 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/409 ,  G11C11/4093 ,  G11C2207/107 ,  G11C2207/108

摘要： A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.

公开(公告)号：US06771108B2

公开(公告)日：2004-08-03

申请号：US10152614

申请日：2002-05-23

申请人： Kenichi Kawasaki ,  Yasuharu Sato ,  Yasurou Matsuzaki ,  Takaaki Suzuki

发明人： Kenichi Kawasaki ,  Yasuharu Sato ,  Yasurou Matsuzaki ,  Takaaki Suzuki

IPC分类号： H03K300

CPC分类号： G11C7/109 ,  G11C7/1078 ,  G11C7/222 ,  G11C7/225 ,  G11C7/227 ,  G11C11/406 ,  G11C11/40615 ,  H03L7/0814

摘要： An input circuit has an input buffer and a detection circuit. The input buffer receives an external signal and outputs an internal signal. The detection circuit detects whether or not the external signal is provided. The input buffer outputs the internal signal when an output of the detection circuit indicates that the external signal is provided. This arrangement shortens the lock-on time of an internal circuit (synchronous circuit).

摘要翻译： 输入电路具有输入缓冲器和检测电路。 输入缓冲器接收外部信号并输出​​内部信号。 检测电路检测外部信号是否被提供。 当检测电路的输出指示提供外部信号时，输入缓冲器输出内部信号。 这种布置缩短了内部电路（同步电路）的锁定时间。

公开(公告)号：US06636449B2

公开(公告)日：2003-10-21

申请号：US09841611

申请日：2001-04-25

申请人： Yasurou Matsuzaki

发明人： Yasurou Matsuzaki

IPC分类号： G11C700

CPC分类号： G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/4072 ,  G11C11/4094 ,  G11C2211/4061 ,  G11C2211/4065

摘要： According to the present invention, a memory circuit requiring refresh operations a first circuit which receives a command in synchronization with a clock signal, and which generates a first internal command internally and a second circuit which generates a second internal command, i.g. a refresh command, internally in a prescribed refresh cycle. And an internal circuit, according to said first internal command, executes corresponding control through clock-synchronous operations, and when said refresh command is issued, sequentially executes control corresponding to the refresh command and control corresponding to said first internal command through clock-asynchronous operations. According to the present invention, when a refresh timing signal is generated, the refresh operation can be intrupted among the external command operations.

公开(公告)号：US06498524B1

公开(公告)日：2002-12-24

申请号：US09706731

申请日：2000-11-07

申请人： Kenichi Kawasaki ,  Yasuharu Sato ,  Terumasa Kitahara ,  Masao Nakano ,  Masao Taguchi ,  Yoshihiro Takemae ,  Yasurou Matsuzaki ,  Koichi Nishimura ,  Yoshinori Okajima ,  Naoharu Shinozaki ,  Hiroko Douchi

发明人： Kenichi Kawasaki ,  Yasuharu Sato ,  Terumasa Kitahara ,  Masao Nakano ,  Masao Taguchi ,  Yoshihiro Takemae ,  Yasurou Matsuzaki ,  Koichi Nishimura ,  Yoshinori Okajima ,  Naoharu Shinozaki ,  Hiroko Douchi

IPC分类号： H03L708

CPC分类号： G11C7/106 ,  G06F13/4243 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/002 ,  G11C2207/108 ,  H03K5/133 ,  H03K2005/00058 ,  H03L7/0805 ,  H03L7/0814

摘要： Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock. The output timing control circuit includes a delay circuit for delaying the reference signal by a specified magnitude and generating an output timing signal, a phase comparison circuit for comparing the phase of the output timing signal with the phase of the reference signal, and a delay control circuit for specifying the magnitude of a delay to be produced by the delay circuit according to the result of comparison performed by the phase comparison circuit.

摘要翻译： 公开了一种用于输出具有相对于外部时钟保持的给定相位的输出信号的半导体器件，尽管特性差，温度变化和电源电压波动。 该半导体器件包括用于输入外部时钟并输出参考信号的输入电路，用于接收输出定时信号并根据输出定时信号的定时输出输出信号的输出电路和用于控制的输出定时控制电路 输出定时，使得输出信号相对于外部时钟呈现给定的相位。 输出定时控制电路包括用于将参考信号延迟指定幅度并产生输出定时信号的延迟电路，用于将输出定时信号的相位与参考信号的相位进行比较的相位比较电路和延迟控制 电路，用于根据由相位比较电路执行的比较结果来指定由延迟电路产生的延迟的大小。

公开(公告)号：US06298004B1

公开(公告)日：2001-10-02

申请号：US08892790

申请日：1997-07-15

申请人： Kenichi Kawasaki ,  Yasuharu Sato ,  Terumasa Kitahara ,  Masao Nakano ,  Masao Taguchi ,  Yoshihiro Takemae ,  Yasurou Matsuzaki ,  Koichi Nishimura ,  Yoshinori Okajima ,  Naoharu Shinozaki ,  Hiroko Douchi

发明人： Kenichi Kawasaki ,  Yasuharu Sato ,  Terumasa Kitahara ,  Masao Nakano ,  Masao Taguchi ,  Yoshihiro Takemae ,  Yasurou Matsuzaki ,  Koichi Nishimura ,  Yoshinori Okajima ,  Naoharu Shinozaki ,  Hiroko Douchi

IPC分类号： G11C800

CPC分类号： G11C7/106 ,  G06F13/4243 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/002 ,  G11C2207/108 ,  H03K5/133 ,  H03K2005/00058 ,  H03L7/0805 ,  H03L7/0814

摘要： Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock. The output timing control circuit includes a delay circuit for delaying the reference signal by a specified magnitude and generating an output timing signal, a phase comparison circuit for comparing the phase of the output timing signal with the phase of the reference signal, and a delay control circuit for specifying the magnitude of a delay to be produced by the delay circuit according to the result of comparison performed by the phase comparison circuit.

摘要翻译： 公开了一种用于输出具有相对于外部时钟保持的给定相位的输出信号的半导体器件，尽管特性差，温度变化和电源电压波动。 该半导体器件包括用于输入外部时钟并输出参考信号的输入电路，用于接收输出定时信号并根据输出定时信号的定时输出输出信号的输出电路和用于控制的输出定时控制电路 输出定时，使得输出信号相对于外部时钟呈现给定的相位。 输出定时控制电路包括用于将参考信号延迟指定幅度并产生输出定时信号的延迟电路，用于将输出定时信号的相位与参考信号的相位进行比较的相位比较电路和延迟控制 电路，用于根据由相位比较电路执行的比较结果来指定由延迟电路产生的延迟的大小。

公开(公告)号：US06185149B2

公开(公告)日：2001-02-06

申请号：US09340147

申请日：1999-06-28

申请人： Shinya Fujioka ,  Masao Taguchi ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Yasurou Matsuzaki ,  Toshiya Uchida

发明人： Shinya Fujioka ,  Masao Taguchi ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Yasurou Matsuzaki ,  Toshiya Uchida

IPC分类号： G11C800

CPC分类号： G11C7/1018 ,  G11C7/1072

摘要： A semiconductor memory includes memory cell blocks, a burst-length information generating circuit which generates burst-length information based on a burst length, and a block enable circuit which receives the burst-length information. The block enable circuit selectively enables one of the memory cell blocks when the burst length is equal to or shorter than a predetermined burst length and selectively enables a plurality of memory cell blocks based on the burst length when the burst length is longer than the predetermined burst length. Data are read from the above-mentioned one or plurality of memory cell blocks.

摘要翻译： 半导体存储器包括存储单元块，基于突发长度生成突发长度信息的突发长度信息产生电路，以及接收脉冲串长度信息的块使能电路。 当突发长度等于或小于预定突发长度时，块使能电路选择性地启用存储单元块中的一个，并且当突发长度长于预定突发时，基于脉冲串长度选择性地启用多个存储单元块 长度。 从上述一个或多个存储单元块读取数据。