公开(公告)号：US20200310527A1

公开(公告)日：2020-10-01

申请号：US16370950

申请日：2019-03-30

申请人： Alexander Gendler ,  Yoni Aizik ,  Chen Ranel ,  Ido Melamed ,  Edward Vaiberman

发明人： Alexander Gendler ,  Yoni Aizik ,  Chen Ranel ,  Ido Melamed ,  Edward Vaiberman

IPC分类号： G06F1/3296

摘要： Embodiments include an autonomous core perimeter, configured to save the state of a core of a multi-core processor prior to the processor package being placed into a low-power state. The autonomous core perimeter of each core is configured to save an image of a microcontroller firmware to an external store if it has not been previously saved by another core, along with the unique working state information of that core's microcontroller. Upon restore, the single microcontroller firmware image is retrieved from the external store and pushed to each core along with each core's unique working state.

公开(公告)号：US20170371399A1

公开(公告)日：2017-12-28

申请号：US15190377

申请日：2016-06-23

申请人： Eliezer Weissmann ,  Efraim Rotem ,  Yoni Aizik ,  Doron Rajwan ,  Gal Leibovich ,  Nadav Shulman ,  Hisham Abu Salah

发明人： Eliezer Weissmann ,  Efraim Rotem ,  Yoni Aizik ,  Doron Rajwan ,  Gal Leibovich ,  Nadav Shulman ,  Hisham Abu Salah

IPC分类号： G06F1/32 ,  G06F13/24 ,  G06F1/26

CPC分类号： G06F1/3287 ,  G06F1/266 ,  G06F13/24 ,  Y02D10/14

摘要： In one embodiment, a processor includes a plurality of cores and a power controller including a first logic, responsive to a determination that the processor resided in a forced idle state for less than a threshold duration, to update a first counter and, responsive to a value of the first counter that exceeds a control threshold, prevent the processor from entry into the forced idle state. Other embodiments are described and claimed.

公开(公告)号：US20140006001A1

公开(公告)日：2014-01-02

申请号：US13534713

申请日：2012-06-27

申请人： Gila Kamhi ,  Amit Moran ,  Limor David ,  Yoni Aizik

发明人： Gila Kamhi ,  Amit Moran ,  Limor David ,  Yoni Aizik

IPC分类号： G06F9/455

CPC分类号： G06F9/455 ,  G06F11/3414 ,  G06F11/3461

摘要： Methods, apparatuses and storage medium associated with engineering perceptual computing systems that includes user intent modeling are disclosed herewith. In embodiments, one or more storage medium may include instructions configured to enable a computing device to receive a usage model having a plurality of user event/behavior statistics, and to generate a plurality of traces of user events/behaviors over a period of time to form a workload. The generation may be based at least in part on the user event/behavior statistics. The workload may be for input into an emulator configured to emulate a perceptual computing system. Other embodiments may be disclosed or claimed.

摘要翻译： 本文公开了与包括用户意图建模的工程感知计算系统相关联的方法，装置和存储介质。 在实施例中，一个或多个存储介质可以包括被配置为使得计算设备能够接收具有多个用户事件/行为统计信息的使用模型并且在一段时间内生成用户事件/行为的多个痕迹的指令 形成工作量。 这一代可以至少部分地基于用户事件/行为统计。 工作负载可以用于输入到被配置为模拟感知计算系统的仿真器中。 可以公开或要求保护其他实施例。

公开(公告)号：US20190286223A1

公开(公告)日：2019-09-19

申请号：US16369113

申请日：2019-03-29

申请人： Ben Furman ,  Yoni Aizik ,  Robert P. Adler ,  Robert Hesse ,  Chen Ranel

发明人： Ben Furman ,  Yoni Aizik ,  Robert P. Adler ,  Robert Hesse ,  Chen Ranel

IPC分类号： G06F1/3296 ,  G06F1/3287 ,  G06F9/30 ,  G06F15/78

摘要： In one embodiment, an apparatus includes a bulk write circuit to generate a bulk write message to send to a destination agent to cause the destination agent to write data comprising register contents into a plurality of registers, at least some of the plurality of registers comprising non-consecutive registers. The bulk write message may include a first message header, a first chunk header including an address of a first register of a first subset of the plurality of registers, and a first payload portion having the register contents for the first subset of the plurality of registers. Other embodiments are described and claimed.

公开(公告)号：US20190004582A1

公开(公告)日：2019-01-03

申请号：US15635307

申请日：2017-06-28

申请人： Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nir Rosenzweig ,  Yoni Aizik

发明人： Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nir Rosenzweig ,  Yoni Aizik

IPC分类号： G06F1/32

CPC分类号： G06F1/324 ,  G06F1/3296

摘要： In one embodiment, a processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator. Other embodiments are described and claimed.

公开(公告)号：US20150355705A1

公开(公告)日：2015-12-10

申请号：US14298171

申请日：2014-06-06

申请人： Eliezer Weissmann ,  Yoni Aizik ,  Doron Rajwan ,  Nir Rosenzweig ,  Efraim Rotem ,  Barnes Cooper ,  Paul S. Diefenbaugh ,  Guy M. Therien ,  Michael Mishaeli ,  Nadav Shulman ,  Ido Melamed ,  Niv Tokman ,  Alexander Gendler ,  Arik Gihon ,  Yevgeni Sabin ,  Hisham Abu Salah ,  Esfir Natanzon

发明人： Eliezer Weissmann ,  Yoni Aizik ,  Doron Rajwan ,  Nir Rosenzweig ,  Efraim Rotem ,  Barnes Cooper ,  Paul S. Diefenbaugh ,  Guy M. Therien ,  Michael Mishaeli ,  Nadav Shulman ,  Ido Melamed ,  Niv Tokman ,  Alexander Gendler ,  Arik Gihon ,  Yevgeni Sabin ,  Hisham Abu Salah ,  Esfir Natanzon

IPC分类号： G06F1/32

CPC分类号： G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F11/0757 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D50/20

摘要： In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括多个核心和功率控制器。 功率控制器可以包括硬件占空比（HDC）逻辑，以便即使逻辑处理器具有要执行的工作负载来使得一个核的至少一个逻辑处理器进入强制空闲状态。 此外，如果至少另外一个其他逻辑处理器被阻止进入强制空闲状态，则HDC逻辑可以导致逻辑处理器在空闲周期结束之前退出强制空闲状态。 描述和要求保护其他实施例。

公开(公告)号：US09152440B2

公开(公告)日：2015-10-06

申请号：US13534713

申请日：2012-06-27

申请人： Gila Kamhi ,  Amit Moran ,  Limor David ,  Yoni Aizik

发明人： Gila Kamhi ,  Amit Moran ,  Limor David ,  Yoni Aizik

IPC分类号： G06F9/455 ,  G06F11/34

CPC分类号： G06F9/455 ,  G06F11/3414 ,  G06F11/3461

摘要： Methods, apparatuses and storage medium associated with engineering perceptual computing systems that includes user intent modeling are disclosed herewith. In embodiments, one or more storage medium may include instructions configured to enable a computing device to receive a usage model having a plurality of user event/behavior statistics, and to generate a plurality of traces of user events/behaviors over a period of time to form a workload. The generation may be based at least in part on the user event/behavior statistics. The workload may be for input into an emulator configured to emulate a perceptual computing system. Other embodiments may be disclosed or claimed.

摘要翻译： 本文公开了与包括用户意图建模的工程感知计算系统相关联的方法，装置和存储介质。 在实施例中，一个或多个存储介质可以包括被配置为使得计算设备能够接收具有多个用户事件/行为统计信息的使用模型并且在一段时间内生成用户事件/行为的多个痕迹的指令， 形成工作量。 这一代可以至少部分地基于用户事件/行为统计。 工作负载可以用于输入到被配置为模拟感知计算系统的仿真器中。 可以公开或要求保护其他实施例。