公开(公告)号：US20150355705A1

公开(公告)日：2015-12-10

申请号：US14298171

申请日：2014-06-06

申请人： Eliezer Weissmann ,  Yoni Aizik ,  Doron Rajwan ,  Nir Rosenzweig ,  Efraim Rotem ,  Barnes Cooper ,  Paul S. Diefenbaugh ,  Guy M. Therien ,  Michael Mishaeli ,  Nadav Shulman ,  Ido Melamed ,  Niv Tokman ,  Alexander Gendler ,  Arik Gihon ,  Yevgeni Sabin ,  Hisham Abu Salah ,  Esfir Natanzon

发明人： Eliezer Weissmann ,  Yoni Aizik ,  Doron Rajwan ,  Nir Rosenzweig ,  Efraim Rotem ,  Barnes Cooper ,  Paul S. Diefenbaugh ,  Guy M. Therien ,  Michael Mishaeli ,  Nadav Shulman ,  Ido Melamed ,  Niv Tokman ,  Alexander Gendler ,  Arik Gihon ,  Yevgeni Sabin ,  Hisham Abu Salah ,  Esfir Natanzon

IPC分类号： G06F1/32

CPC分类号： G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F11/0757 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D50/20

摘要： In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括多个核心和功率控制器。 功率控制器可以包括硬件占空比（HDC）逻辑，以便即使逻辑处理器具有要执行的工作负载来使得一个核的至少一个逻辑处理器进入强制空闲状态。 此外，如果至少另外一个其他逻辑处理器被阻止进入强制空闲状态，则HDC逻辑可以导致逻辑处理器在空闲周期结束之前退出强制空闲状态。 描述和要求保护其他实施例。

公开(公告)号：US20190196573A1

公开(公告)日：2019-06-27

申请号：US15849995

申请日：2017-12-21

申请人： Nikhil Gupta ,  Israel Hirsh ,  Esfir Natanzon ,  Nir Rosenzweig ,  Efraim Rotem ,  Guy M. Therien ,  Ankush Varma ,  Eliezer Weissmann

发明人： Nikhil Gupta ,  Israel Hirsh ,  Esfir Natanzon ,  Nir Rosenzweig ,  Efraim Rotem ,  Guy M. Therien ,  Ankush Varma ,  Eliezer Weissmann

IPC分类号： G06F1/32 ,  G06F1/28

CPC分类号： G06F1/3293 ,  G06F1/28

摘要： In one embodiment, a processor includes: one or more cores to execute instructions; a first request register to store hardware performance state control information for a first core of the one or more cores obtained from an operating system; a second request register to store hardware performance state control override information, the hardware performance state control override information to be received from a management controller coupled to the processor; and a power controller coupled to the one or more cores to control a performance state of the first core based at least in part on the hardware performance state override information when at least one override indicator of the second request register is set. Other embodiments are described and claimed.

公开(公告)号：US20190204893A1

公开(公告)日：2019-07-04

申请号：US15857802

申请日：2017-12-29

申请人： Efraim Rotem ,  Esfir Natanzon ,  Doron Rajwan ,  Eliezer Weissmann ,  Dorit Shapira ,  Lily P. Looi ,  Bart Plackle ,  Nadav Shulman

发明人： Efraim Rotem ,  Esfir Natanzon ,  Doron Rajwan ,  Eliezer Weissmann ,  Dorit Shapira ,  Lily P. Looi ,  Bart Plackle ,  Nadav Shulman

IPC分类号： G06F1/32 ,  G06F11/30 ,  G06F1/20

CPC分类号： G06F1/324 ,  G06F1/206 ,  G06F11/3024 ,  G06F11/3062

摘要： In one embodiment, a processor includes: at least one core; a stress detector coupled to the at least one core to receive at least one of a voltage and a temperature at which the processor is to operate, calculate an effective stress based at least in part thereon, and maintain an accumulated effective stress; a clock circuit to calculate a lifetime duration of the processor in a platform; a meter to receive the accumulated effective stress, the lifetime duration and a stress model value and generate a control signal based on a comparison of the accumulated effective stress and the stress model value; and a power controller to control at least one parameter of a turbo mode of the processor based at least in part on the control signal. Other embodiments are described and claimed.

公开(公告)号：US20130268742A1

公开(公告)日：2013-10-10

申请号：US13992710

申请日：2011-12-29

申请人： Koichi Yamada ,  Boris Ginzburg ,  Wei Li ,  Ronny Ronen ,  Esfir Natanzon ,  Konstantin Levit-Gurevich ,  Gadi Haber ,  Alon Naveh ,  Eliezer Weissmann ,  Michael Mishaeli

发明人： Koichi Yamada ,  Boris Ginzburg ,  Wei Li ,  Ronny Ronen ,  Esfir Natanzon ,  Konstantin Levit-Gurevich ,  Gadi Haber ,  Alon Naveh ,  Eliezer Weissmann ,  Michael Mishaeli

IPC分类号： G06F9/30

CPC分类号： G06F9/30181 ,  G06F9/5044 ,  G06F9/5094 ,  Y02D10/22

摘要： An asymmetric multiprocessor system (ASMP) may comprise computational cores implementing different instruction set architectures and having different power requirements. Program code executing on the ASMP is analyzed by a binary analysis unit to determine what functions are called by the program code and select which of the cores are to execute the program code, or a code segment thereof. Selection may be made to provide for native execution of the program code, to minimize power consumption, and so forth. Control operations based on this selection may then be inserted into the program code, forming instrumented program code. The instrumented program code is then executed by the ASMP.

摘要翻译： 非对称多处理器系统（ASMP）可以包括实现不同指令集架构并具有不同功率需求的计算核心。 在ASMP上执行的程序代码由二进制分析单元进行分析，以确定程序代码调用哪些函数，并选择哪些核执行程序代码或其代码段。 可以进行选择以提供程序代码的本地执行，以最小化功耗等等。 可以将基于该选择的控制操作插入到程序代码中，形成检测程序代码。 然后由ASMP执行检测的程序代码。

公开(公告)号：US09348594B2

公开(公告)日：2016-05-24

申请号：US13992710

申请日：2011-12-29

申请人： Koichi Yamada ,  Boris Ginzburg ,  Wei Li ,  Ronny Ronen ,  Esfir Natanzon ,  Konstantin Levit-Gurevich ,  Gadi Haber ,  Alon Naveh ,  Eliezer Weissmann ,  Michael Mishaeli

发明人： Koichi Yamada ,  Boris Ginzburg ,  Wei Li ,  Ronny Ronen ,  Esfir Natanzon ,  Konstantin Levit-Gurevich ,  Gadi Haber ,  Alon Naveh ,  Eliezer Weissmann ,  Michael Mishaeli

IPC分类号： G06F9/40 ,  G06F9/30 ,  G06F9/50

CPC分类号： G06F9/30181 ,  G06F9/5044 ,  G06F9/5094 ,  Y02D10/22

摘要： An asymmetric multiprocessor system (ASMP) may comprise computational cores implementing different instruction set architectures and having different power requirements. Program code executing on the ASMP is analyzed by a binary analysis unit to determine what functions are called by the program code and select which of the cores are to execute the program code, or a code segment thereof. Selection may be made to provide for native execution of the program code, to minimize power consumption, and so forth. Control operations based on this selection may then be inserted into the program code, forming instrumented program code. The instrumented program code is then executed by the ASMP.

摘要翻译： 非对称多处理器系统（ASMP）可以包括实现不同指令集架构并具有不同功率需求的计算核心。 在ASMP上执行的程序代码由二进制分析单元进行分析，以确定程序代码调用哪些函数，并选择哪些核执行程序代码或其代码段。 可以进行选择以提供程序代码的本地执行，以最小化功耗等等。 可以将基于该选择的控制操作插入到程序代码中，形成检测程序代码。 然后由ASMP执行检测的程序代码。

公开(公告)号：US20140019723A1

公开(公告)日：2014-01-16

申请号：US13993042

申请日：2011-12-28

申请人： Koichi Yamada ,  Ronny Ronen ,  Wei Li ,  Boris Ginzburg ,  Gadi Haber ,  Konstantin Levit-Gurevich ,  Esfir Natanzon ,  Alon Naveh ,  Eliezer Weissmann ,  Michael Mishaeli

发明人： Koichi Yamada ,  Ronny Ronen ,  Wei Li ,  Boris Ginzburg ,  Gadi Haber ,  Konstantin Levit-Gurevich ,  Esfir Natanzon ,  Alon Naveh ,  Eliezer Weissmann ,  Michael Mishaeli

IPC分类号： G06F9/30

CPC分类号： G06F9/30145 ,  G06F1/3243 ,  G06F1/3293 ,  G06F9/30174 ,  G06F9/3808 ,  G06F9/4552 ,  G06F9/5094 ,  G06F15/7807 ,  Y02D10/122 ,  Y02D10/152 ,  Y02D10/22

摘要： An asymmetric multiprocessor system (ASMP) may comprise computational cores implementing different instruction set architectures and having different power requirements. Program code for execution on the ASMP is analyzed and a determination is made as to whether to allow the program code, or a code segment thereof to execute on a first core natively or to use binary translation on the code and execute the translated code on a second core which consumes less power than the first core during execution.

摘要翻译： 非对称多处理器系统（ASMP）可以包括实现不同指令集架构并具有不同功率需求的计算核心。 分析用于在ASMP上执行的程序代码，并且确定是否允许程序代码或其代码段在本地上在第一核上执行或者对代码使用二进制转换并且在 在执行过程中消耗的功率比第一个核心少的第二个核心。

公开(公告)号：US20120233439A1

公开(公告)日：2012-09-13

申请号：US13045688

申请日：2011-03-11

申请人： Boris Ginzburg ,  Esfir Natanzon ,  Ilya Osadchiy ,  Ronny Ronen ,  Eliezer Weissmann ,  Yoav Zach ,  Robert L. Farrell

发明人： Boris Ginzburg ,  Esfir Natanzon ,  Ilya Osadchiy ,  Ronny Ronen ,  Eliezer Weissmann ,  Yoav Zach ,  Robert L. Farrell

IPC分类号： G06F12/10

CPC分类号： G06F12/1027 ,  G06F12/1036 ,  G06F12/109 ,  G06F2212/302 ,  G06F2212/682

摘要： Page faults arising in a graphics processing unit may be handled by an operating system running on the central processing unit. In some embodiments, this means that unpinned memory can be used for the graphics processing unit. Using unpinned memory in the graphics processing unit may expand the capabilities of the graphics processing unit in some cases.

摘要翻译： 在图形处理单元中出现的页面错误可以由在中央处理单元上运行的操作系统来处理。 在一些实施例中，这意味着未被固定的存储器可以用于图形处理单元。 在图形处理单元中使用未固定的存储器可以在某些情况下扩展图形处理单元的能力。

公开(公告)号：US20120236010A1

公开(公告)日：2012-09-20

申请号：US13048053

申请日：2011-03-15

申请人： Boris Ginzburg ,  Esfir Natanzon ,  Ilya Osadchiy ,  Ronny Ronen ,  Eliezer Weissmann ,  Yoav Zach ,  Robert L. Farrell

发明人： Boris Ginzburg ,  Esfir Natanzon ,  Ilya Osadchiy ,  Ronny Ronen ,  Eliezer Weissmann ,  Yoav Zach ,  Robert L. Farrell

IPC分类号： G06F15/16

CPC分类号： G06F12/08 ,  G06F2212/302

摘要： Page faults arising in a graphics processing unit may be handled by an operating system running on the central processing unit. In some embodiments, this means that unpinned memory can be used for the graphics processing unit. Using unpinned memory in the graphics processing unit may expand the capabilities of the graphics processing unit in some cases.

摘要翻译： 在图形处理单元中出现的页面错误可以由在中央处理单元上运行的操作系统来处理。 在一些实施例中，这意味着未被固定的存储器可以用于图形处理单元。 在图形处理单元中使用未固定的存储器可以在某些情况下扩展图形处理单元的能力。

公开(公告)号：US09141361B2

公开(公告)日：2015-09-22

申请号：US13632089

申请日：2012-09-30

申请人： Gadi Haber ,  Konstantin Kostya Levit-Gurevich ,  Esfir Natanzon ,  Boris Ginzburg ,  Aya Elhanan ,  Moshe Maury Bach ,  Igor Breger

发明人： Gadi Haber ,  Konstantin Kostya Levit-Gurevich ,  Esfir Natanzon ,  Boris Ginzburg ,  Aya Elhanan ,  Moshe Maury Bach ,  Igor Breger

IPC分类号： G06F9/30 ,  G06F9/45 ,  G06F9/455 ,  G06F11/36

CPC分类号： G06F9/30181 ,  G06F8/52 ,  G06F9/30145 ,  G06F9/45558 ,  G06F9/467 ,  G06F12/0875 ,  G06F2212/452

摘要： Methods, apparatus and systems for virtualization of a native instruction set are disclosed. Embodiments include a processor core executing the native instructions and a second core, or alternatively only the second processor core consuming less power while executing a second instruction set that excludes portions of the native instruction set. The second core's decoder detects invalid opcodes of the second instruction set. A microcode layer disassembler determines if opcodes should be translated. A translation runtime environment identifies an executable region containing an invalid opcode, other invalid opcodes and interjacent valid opcodes of the second instruction set. An analysis unit determines an initial machine state prior to execution of the invalid opcode. A partial translation of the executable region that includes encapsulations of the translations of invalid opcodes and state recoveries of the machine states is generated and saved to a translation cache memory.

摘要翻译： 公开了用于本地指令集的虚拟化的方法，装置和系统。 实施例包括执行本地指令的处理器核心和第二核心，或者替代地，只有第二处理器核心在执行排除本地指令集的部分的第二指令集时消耗较少的功率。 第二核心解码器检测第二指令集的无效操作码。 微码层拆解器确定是否应翻译操作码。 翻译运行时环境识别包含第二指令集的无效操作码，其他无效操作码和中间有效操作码的可执行区域。 分析单元在执行无效操作码之前确定初始机器状态。 生成可执行区域的部分翻译，其中包括无效操作码的翻译和机器状态的状态恢复的封装，并将其保存到翻译高速缓冲存储器。

公开(公告)号：US20170132007A1

公开(公告)日：2017-05-11

申请号：US15412565

申请日：2017-01-23

申请人： Gadi Haber ,  Konstantin Kostya Levit-Gurevich ,  Esfir Natanzon ,  Boris Ginzburg ,  Aya Elhanan ,  Moshe Maury Bach ,  Igor Breger

发明人： Gadi Haber ,  Konstantin Kostya Levit-Gurevich ,  Esfir Natanzon ,  Boris Ginzburg ,  Aya Elhanan ,  Moshe Maury Bach ,  Igor Breger

IPC分类号： G06F9/30 ,  G06F9/46

CPC分类号： G06F9/30181 ,  G06F8/52 ,  G06F9/30145 ,  G06F9/45558 ,  G06F9/467 ,  G06F12/0875 ,  G06F2212/452

摘要： Methods, apparatus and systems for virtualization of a native instruction set are disclosed. Embodiments include a processor core executing the native instructions and a second core, or alternatively only the second processor core consuming less power while executing a second instruction set that excludes portions of the native instruction set. The second core's decoder detects invalid opcodes of the second instruction set. A microcode layer disassembler determines if opcodes should be translated. A translation runtime environment identifies an executable region containing an invalid opcode, other invalid opcodes and interjacent valid opcodes of the second instruction set. An analysis unit determines an initial machine state prior to execution of the invalid opcode. A partial translation of the executable region that includes encapsulations of the translations of invalid opcodes and state recoveries of the machine states is generated and saved to a translation cache memory.