公开(公告)号：US20150355705A1

公开(公告)日：2015-12-10

申请号：US14298171

申请日：2014-06-06

申请人： Eliezer Weissmann ,  Yoni Aizik ,  Doron Rajwan ,  Nir Rosenzweig ,  Efraim Rotem ,  Barnes Cooper ,  Paul S. Diefenbaugh ,  Guy M. Therien ,  Michael Mishaeli ,  Nadav Shulman ,  Ido Melamed ,  Niv Tokman ,  Alexander Gendler ,  Arik Gihon ,  Yevgeni Sabin ,  Hisham Abu Salah ,  Esfir Natanzon

发明人： Eliezer Weissmann ,  Yoni Aizik ,  Doron Rajwan ,  Nir Rosenzweig ,  Efraim Rotem ,  Barnes Cooper ,  Paul S. Diefenbaugh ,  Guy M. Therien ,  Michael Mishaeli ,  Nadav Shulman ,  Ido Melamed ,  Niv Tokman ,  Alexander Gendler ,  Arik Gihon ,  Yevgeni Sabin ,  Hisham Abu Salah ,  Esfir Natanzon

IPC分类号： G06F1/32

CPC分类号： G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F11/0757 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D50/20

摘要： In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括多个核心和功率控制器。 功率控制器可以包括硬件占空比（HDC）逻辑，以便即使逻辑处理器具有要执行的工作负载来使得一个核的至少一个逻辑处理器进入强制空闲状态。 此外，如果至少另外一个其他逻辑处理器被阻止进入强制空闲状态，则HDC逻辑可以导致逻辑处理器在空闲周期结束之前退出强制空闲状态。 描述和要求保护其他实施例。

公开(公告)号：US20170371399A1

公开(公告)日：2017-12-28

申请号：US15190377

申请日：2016-06-23

申请人： Eliezer Weissmann ,  Efraim Rotem ,  Yoni Aizik ,  Doron Rajwan ,  Gal Leibovich ,  Nadav Shulman ,  Hisham Abu Salah

发明人： Eliezer Weissmann ,  Efraim Rotem ,  Yoni Aizik ,  Doron Rajwan ,  Gal Leibovich ,  Nadav Shulman ,  Hisham Abu Salah

IPC分类号： G06F1/32 ,  G06F13/24 ,  G06F1/26

CPC分类号： G06F1/3287 ,  G06F1/266 ,  G06F13/24 ,  Y02D10/14

摘要： In one embodiment, a processor includes a plurality of cores and a power controller including a first logic, responsive to a determination that the processor resided in a forced idle state for less than a threshold duration, to update a first counter and, responsive to a value of the first counter that exceeds a control threshold, prevent the processor from entry into the forced idle state. Other embodiments are described and claimed.

公开(公告)号：US09158693B2

公开(公告)日：2015-10-13

申请号：US13285465

申请日：2011-10-31

申请人： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Hisham Abu-Salah

发明人： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Hisham Abu-Salah

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F1/3275 ,  G06F1/28 ,  G06F1/3287 ,  G06F12/0802 ,  G06F12/084 ,  G06F12/0848 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/282 ,  G06F2212/502 ,  G06F2212/621 ,  Y02D10/13

摘要： In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明涉及具有多个核心的处理器和耦合到核心并且包括多个分区的高速缓冲存储器。 处理器还可以包括基于在至少一个核上执行的工作负载的存储器有界性来动态地改变高速缓存存储器的大小的逻辑。 描述和要求保护其他实施例。

公开(公告)号：US20190004582A1

公开(公告)日：2019-01-03

申请号：US15635307

申请日：2017-06-28

申请人： Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nir Rosenzweig ,  Yoni Aizik

发明人： Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nir Rosenzweig ,  Yoni Aizik

IPC分类号： G06F1/32

CPC分类号： G06F1/324 ,  G06F1/3296

摘要： In one embodiment, a processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator. Other embodiments are described and claimed.

公开(公告)号：US20190196573A1

公开(公告)日：2019-06-27

申请号：US15849995

申请日：2017-12-21

申请人： Nikhil Gupta ,  Israel Hirsh ,  Esfir Natanzon ,  Nir Rosenzweig ,  Efraim Rotem ,  Guy M. Therien ,  Ankush Varma ,  Eliezer Weissmann

发明人： Nikhil Gupta ,  Israel Hirsh ,  Esfir Natanzon ,  Nir Rosenzweig ,  Efraim Rotem ,  Guy M. Therien ,  Ankush Varma ,  Eliezer Weissmann

IPC分类号： G06F1/32 ,  G06F1/28

CPC分类号： G06F1/3293 ,  G06F1/28

摘要： In one embodiment, a processor includes: one or more cores to execute instructions; a first request register to store hardware performance state control information for a first core of the one or more cores obtained from an operating system; a second request register to store hardware performance state control override information, the hardware performance state control override information to be received from a management controller coupled to the processor; and a power controller coupled to the one or more cores to control a performance state of the first core based at least in part on the hardware performance state override information when at least one override indicator of the second request register is set. Other embodiments are described and claimed.

公开(公告)号：US20190204893A1

公开(公告)日：2019-07-04

申请号：US15857802

申请日：2017-12-29

申请人： Efraim Rotem ,  Esfir Natanzon ,  Doron Rajwan ,  Eliezer Weissmann ,  Dorit Shapira ,  Lily P. Looi ,  Bart Plackle ,  Nadav Shulman

发明人： Efraim Rotem ,  Esfir Natanzon ,  Doron Rajwan ,  Eliezer Weissmann ,  Dorit Shapira ,  Lily P. Looi ,  Bart Plackle ,  Nadav Shulman

IPC分类号： G06F1/32 ,  G06F11/30 ,  G06F1/20

CPC分类号： G06F1/324 ,  G06F1/206 ,  G06F11/3024 ,  G06F11/3062

摘要： In one embodiment, a processor includes: at least one core; a stress detector coupled to the at least one core to receive at least one of a voltage and a temperature at which the processor is to operate, calculate an effective stress based at least in part thereon, and maintain an accumulated effective stress; a clock circuit to calculate a lifetime duration of the processor in a platform; a meter to receive the accumulated effective stress, the lifetime duration and a stress model value and generate a control signal based on a comparison of the accumulated effective stress and the stress model value; and a power controller to control at least one parameter of a turbo mode of the processor based at least in part on the control signal. Other embodiments are described and claimed.

公开(公告)号：US09092210B2

公开(公告)日：2015-07-28

申请号：US13307529

申请日：2011-11-30

申请人： Efraim Rotem ,  Nir Rosenzweig ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Eliezer Weissmann ,  Michael Zelikson

发明人： Efraim Rotem ,  Nir Rosenzweig ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Eliezer Weissmann ,  Michael Zelikson

IPC分类号： G06F1/30 ,  G06F1/28 ,  G06F1/32

CPC分类号： G06F1/30 ,  G06F1/28 ,  G06F1/3206

摘要： In one embodiment, a processor includes a core with a front end unit, at least one execution unit, and a back end unit. Multiple voltage drop detectors can be located within the core each to output a voltage drop signal when a detected voltage falls below a threshold voltage. In turn, a current transient logic coupled to receive the voltage drop signals can control a micro-architectural parameter of at least one of the front end unit, execution unit and back end unit responsive to receipt of a voltage drop signal. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括具有前端单元的核心，至少一个执行单元和后端单元。 当检测到的电压低于阈值电压时，多个电压降检测器可以位于每个核心内以输出电压降信号。 反过来，耦合以接收电压降信号的电流瞬态逻辑可以响应于接收到电压降信号而控制前端单元，执行单元和后端单元中的至少一个的微架构参数。 描述和要求保护其他实施例。

公开(公告)号：US20120166854A1

公开(公告)日：2012-06-28

申请号：US13307529

申请日：2011-11-30

申请人： Efraim Rotem ,  Nir Rosenzweig ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Eliezer Weissmann ,  Michael Zelikson

发明人： Efraim Rotem ,  Nir Rosenzweig ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Eliezer Weissmann ,  Michael Zelikson

IPC分类号： G06F1/26

CPC分类号： G06F1/30 ,  G06F1/28 ,  G06F1/3206

摘要： In one embodiment, a processor includes a core with a front end unit, at least one execution unit, and a back end unit. Multiple voltage drop detectors can be located within the core each to output a voltage drop signal when a detected voltage falls below a threshold voltage. In turn, a current transient logic coupled to receive the voltage drop signals can control a micro-architectural parameter of at least one of the front end unit, execution unit and back end unit responsive to receipt of a voltage drop signal. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括具有前端单元的核心，至少一个执行单元和后端单元。 当检测到的电压低于阈值电压时，多个电压降检测器可以位于每个核心内以输出电压降信号。 反过来，耦合以接收电压降信号的电流瞬态逻辑可以响应于接收到电压降信号而控制前端单元，执行单元和后端单元中的至少一个的微架构参数。 描述和要求保护其他实施例。

公开(公告)号：US20160026479A1

公开(公告)日：2016-01-28

申请号：US14338692

申请日：2014-07-23

申请人： Nir Rosenzweig ,  Efraim Rotem ,  Doron Rajwan ,  Nadav Shulman ,  Eliezer Weissmann

发明人： Nir Rosenzweig ,  Efraim Rotem ,  Doron Rajwan ,  Nadav Shulman ,  Eliezer Weissmann

IPC分类号： G06F9/445 ,  G06F13/42 ,  G06F12/08

CPC分类号： G06F9/44505 ,  G06F1/324 ,  G06F12/0844 ,  G06F13/4234 ,  G06F2212/1052 ,  G06F2212/604 ,  Y02D10/14 ,  Y02D10/151

摘要： In an embodiment, a processor includes at least one core and an interconnect that couples the at least one core and the cache memory. The interconnect is to operate at an interconnect frequency (fCL). The processor also includes a power management unit (PMU) including fCL logic to determine whether to adjust the fCL responsive to a Bayesian prediction value that is associated with scalability of a workload to be processed by the processor. The Bayesian prediction value may be determined based on one or more activity measures associated with the processor. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括耦合至少一个核心和高速缓冲存储器的至少一个核心和互连。 互连以互连频率（fCL）运行。 处理器还包括功率管理单元（PMU），其包括fCL逻辑以确定是否响应于与要由处理器处理的工作负载的可伸缩性相关联的贝叶斯预测值来调整fCL。 可以基于与处理器相关联的一个或多个活动度量来确定贝叶斯预测值。 描述和要求保护其他实施例。

公开(公告)号：US20180336111A1

公开(公告)日：2018-11-22

申请号：US15599587

申请日：2017-05-19

申请人： Alexander Gendler ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Michael Mishaeli ,  Ilya Zegelman ,  Krishnakanth V. Sistla

发明人： Alexander Gendler ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Michael Mishaeli ,  Ilya Zegelman ,  Krishnakanth V. Sistla

IPC分类号： G06F11/22 ,  G06F1/32 ,  G06F13/16 ,  G06F11/27

CPC分类号： G06F11/2284 ,  G06F1/3287 ,  G06F1/3296 ,  G06F11/2236 ,  G06F11/27 ,  G06F11/321 ,  G06F13/1663

摘要： In one embodiment, a processor includes a core and a power controller coupled to the core that in turn includes a self-test control circuit. The self-test circuit is adapted to: isolate the core during field operation; cause the core to execute at least one diagnostic test at a first operating voltage to identify a guard band voltage for the core; and cause the core to enter into a low power state after the execution of the at least one diagnostic test. Other embodiments are described and claimed.