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1.发明申请Bridging centrality: a concept and formula to identify bridging nodes in scale-free networks 失效桥接中心性：确定无大规模网络中的桥接节点的概念和公式公开(公告)号：US20070286218A1
公开(公告)日：2007-12-13
申请号：US11804700
申请日：2007-05-18
IPC分类号： H04L12/66
CPC分类号： H04L45/123 , H04L41/12 , H04L41/145 , H04L41/16
摘要： A method for identifying a bridge node in a network using a processor and memory unit in a specially programmed special purpose-purpose computer including the steps of, for each node in a plurality of nodes in the network: determining a global metric proportional to total traffic flow in the network and through the node; determining a local metric proportional to traffic flow between the node and each second node in the network connected to the node and traffic flow between each second node and each third node in the network connected to a second node; determining a second local metric proportional to the respective traffic flows between each node and each second node; and calculating a respective combination of the global metric and the first and second local metrics; and selecting, a bridge node from among the plurality of nodes based on the respective combinations.
摘要翻译： 一种用于使用专门编程的特殊用途计算机中的处理器和存储器单元来识别网络中的网桥节点的方法，包括以下步骤：针对网络中的多个节点中的每个节点：确定与总流量成比例的全局度量 流经网络并通过节点; 确定与连接到节点的网络中的节点与每个第二节点之间的业务流量成比例的本地度量，以及连接到第二节点的网络中每个第二节点与每个第三节点之间的业务流; 确定与每个节点和每个第二节点之间的相应业务流成比例的第二本地度量; 以及计算所述全局度量和所述第一和第二局部度量的相应组合; 以及基于各个组合从多个节点中选择一个桥接节点。
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2.发明授权Chip-size packages assembled using mass production techniques at the wafer-level 失效芯片尺寸封装使用大量生产技术在晶圆级组装
公开(公告)号：US6004867A
公开(公告)日：1999-12-21
申请号：US990070
申请日：1997-12-12
申请人： Sam Il Kim , Young Rae Cho
发明人： Sam Il Kim , Young Rae Cho
CPC分类号： H01L24/81 , H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L2224/13144 , H01L2224/81801 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/30107
摘要： A chip-size package includes a semiconductor chip having a plurality of input/output pads on an active surface and a passivation layer covering the active surface such that the pads are exposed. Attached to the chip is a substrate having a plurality of electrically conductive traces and corresponding terminal pads therein. A bottom portion of each of the traces is exposed at the bottom surface of the substrate so that the traces are mechanically and electrically bonded to one of the input/output pads. The terminal pads are formed on a top portion of each of the traces and are exposed to a top surface of the substrate. Accordingly, the terminal pads are not limited to being located over the center or the periphery of the chip where the input/output pads are located, but rather can be arranged over the entire area of the chip to produce a chip-size package capable of mass production.
摘要翻译： 芯片尺寸封装包括在有源表面上具有多个输入/输出焊盘的半导体芯片和覆盖有源表面的钝化层，使得焊盘露出。 连接到芯片的是具有多个导电迹线和相应的端子焊盘的衬底。 每个迹线的底部暴露在基板的底表面处，使得迹线机械地和电气地结合到输入/输出焊盘之一。 端子焊盘形成在每个迹线的顶部上并暴露于衬底的顶表面。 因此，端子焊盘不限于位于输入/输出焊盘所在芯片的中心或周边上，而是可以布置在芯片的整个区域上，以产生能够 大量生产。
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公开(公告)号：US5844360A
公开(公告)日：1998-12-01
申请号：US703976
申请日：1996-08-28
申请人： Hyo Soo Jeong , Young Rae Cho , Jae Yeol Oh , Moon Jae Do
发明人： Hyo Soo Jeong , Young Rae Cho , Jae Yeol Oh , Moon Jae Do
CPC分类号： H01J29/94 , H01J2201/304 , H01J2209/385 , H01J2329/00
摘要： Evacuation of the volume of a field emission display can be carried out more easily by attaching the auxiliary chamber of various shape to the main space of a field emission display, which enlarge the volume of the field emission display. Several types of auxiliary chambers are attached to the main space of a field emission display and the resultant structures are described. The main purpose of the present invention is to introduce the method of providing the space for placing getters and increasing the conductance of the system to evacuate by enlarging the total volume of the field emission display.
摘要翻译： 可以通过将各种形状的辅助室附接到场致发射显示器的主空间来更容易地进行场致发射显示的体积的抽出，这扩大了场致发射显示的体积。 几种类型的辅助室连接到场发射显示器的主空间，并且描述了所得到的结构。 本发明的主要目的是介绍通过放大场发射显示的总体积来提供放置吸气剂的空间和增加系统疏散的电导的方法。
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公开(公告)号：US06690116B2
公开(公告)日：2004-02-10
申请号：US09872285
申请日：2001-05-31
申请人： Yoon-Ho Song , Young-Rae Cho , Seung-Youl Kang , Moon-Youn Jung , Chi-Sun Hwang , Jin-Ho Lee , Kyoung-Ik Cho
发明人： Yoon-Ho Song , Young-Rae Cho , Seung-Youl Kang , Moon-Youn Jung , Chi-Sun Hwang , Jin-Ho Lee , Kyoung-Ik Cho
IPC分类号： G09G310
CPC分类号： H01J31/127
摘要： A high-resolution field emission display that applies a field emission device (or a field emission array) being an electron source element to a flat panel display device. The field emission display includes an upper plate and a lower plate that face each other, wherein the lower plate and the upper plate are vacuum-packaged in parallel positions. A dot pixel of the lower plate includes a high-voltage amorphous silicon thin film transistor formed on the glass substrate of the lower plate, a diode type field emission film partially formed on the drain of the high-voltage amorphous silicon TFT, a passivation insulation layer formed on the high-voltage amorphous silicon TFT and the lateral side of the diode type field emission film, and an electron beam focusing electrode/light-shading film which vertically overlaps with the high-voltage amorphous silicon TFT on some parts of the passivation insulation layer and is formed on a lateral side of the diode type field emission film. A dot pixel of the upper plate includes a transparent electrode formed on the glass substrate of the upper plate, and a red, green or blue phosphor formed on some parts of the transparent electrode. Therefore, the high-resolution field emission display device can obtain an effect of focusing the electron beam trajectory and a light-shading effect for the TFT at the same time, and thus remarkably enhance the performance and the resolution of the field emission display.
摘要翻译： 一种高分辨率场致发射显示器，其将作为电子源元件的场发射器件（或场致发射阵列）应用于平板显示器件。 场发射显示器包括彼此面对的上板和下板，其中下板和上板被平行地真空包装。 下板的点像素包括形成在下板的玻璃基板上的高压非晶硅薄膜晶体管，部分地形成在高压非晶硅TFT的漏极上的二极管型场致发射膜，钝化绝缘层 在高电压非晶硅TFT上形成的层和二极管型场致发射膜的侧面，以及与钝化的一些部分上的高压非晶硅TFT垂直重叠的电子束聚焦电极/遮光膜 并且形成在二极管型场致发射膜的侧面上。 上板的点像素包括形成在上板的玻璃基板上的透明电极和形成在透明电极的一些部分上的红色，绿色或蓝色荧光体。 因此，高分辨率场致发射显示装置可以同时获得对TFT的电子束轨迹和遮光效果的聚焦效果，从而显着提高场发射显示的性能和分辨率。
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5.发明授权公开(公告)号：US06682383B2
公开(公告)日：2004-01-27
申请号：US09860397
申请日：2001-05-17
申请人： Young-Rae Cho , Jin-Ho Lee , Yoon-Ho Song , Seung-Youl Kang , Moon-Youn Jung , Kyoung-Ik Cho , Do-Hyung Kim , Chi-Sun Hwang
发明人： Young-Rae Cho , Jin-Ho Lee , Yoon-Ho Song , Seung-Youl Kang , Moon-Youn Jung , Kyoung-Ik Cho , Do-Hyung Kim , Chi-Sun Hwang
IPC分类号： H01J1304
CPC分类号： H01J9/025 , H01J2201/30403
摘要： A cathode structure for a field emission device, which is an essential component of a field emission device, and a method of fabricating the same are provided. An emitter material for electron emission constituting cathodes is formed in a particulate emitter, the particulate emitter is formed of a material from which electrons can be easily emitted at a low electric field. A significant advantage of the present invention over a conventional art is that the present invention patterns an emitter material to a cathode electrode using a photolithography process or a lift-off process. In the lift-off process, the emitting compound is patterned using a sacrifice layer. Also, in another embodiment of the present invention, there is disclosed a method of easily fabricating cathodes for a triode-type field emission device using a particulate emitter material at a low process temperature. Therefore, the present invention provides a method of fabricating a cathode for a triode-type field emission device using particulate emitter that is synthesized at a high temperature of 600° C. over, as the emitter material.
摘要翻译： 提供了场致发射器件的阴极结构及其制造方法。 用于形成阴极的电子发射用发射体材料形成在颗粒状发射体中，微粒发射体由电子能够以低电场容易地发射的材料形成。 本发明相对于传统技术的显着优点是本发明使用光刻工艺或剥离工艺将发射极材料图案化成阴极电极。 在剥离过程中，使用牺牲层对发光化合物进行图案化。 此外，在本发明的另一个实施例中，公开了一种在低工艺温度下使用颗粒发射体材料容易地制造用于三极管型场致发射器件的阴极的方法。 因此，本发明提供一种使用在600℃的高温下合成的粒子发射体作为发射极材料的三极管型场致发射器件的阴极的制造方法。
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公开(公告)号：US5842897A
公开(公告)日：1998-12-01
申请号：US603299
申请日：1996-02-20
申请人： Hyo Soo Jeong , Young Rae Cho , Jae Yeol Oh
发明人： Hyo Soo Jeong , Young Rae Cho , Jae Yeol Oh
CPC分类号： H01J9/242 , H01J29/864 , H01J31/127 , H01J2329/863
摘要： The invention is to provide the method for fabricating the spacers which are mechanically strong and have lower outgassing rate. Spacers in this invention are made of photosensitive glass. A net shaped photosensitive glass is etched by a first photolithography process and then the side wall of it is etched again by a second photolithography process for improving the efficiency of evacuation of the internal cavity of an FED.
摘要翻译： 本发明提供制造间隔物的方法，其具有机械强度并且具有较低的除气速率。 本发明的隔片由感光玻璃制成。 通过第一光刻工艺蚀刻网状感光玻璃，然后通过第二光刻工艺再次蚀刻其侧壁，以提高FED内腔的排空效率。
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7.发明授权
公开(公告)号：US5729086A
公开(公告)日：1998-03-17
申请号：US603303
申请日：1996-02-20
申请人： Hyo Soo Jeong , Young Rae Cho , Jae Yeol Oh , Je Do Mun
发明人： Hyo Soo Jeong , Young Rae Cho , Jae Yeol Oh , Je Do Mun
CPC分类号： H01J29/94 , H01J31/127 , H01J2209/385 , H01J2329/8625
摘要： This invention describes the new structure of a field emission cathode based flat panel display that comprises a main space and an attached auxiliary space, whose volume is larger than that of the main space. In this structure evacuation of the volume of the FED can be carried out more easily. Also getters to eliminate a build up of pressure after sealing off process can be included in the auxiliary tank and high vacuum can be maintained for the lifetime of the FED.
摘要翻译： 本发明描述了一种场发射阴极基平板显示器的新结构，其包括主空间和附加的辅助空间，其体积大于主空间的体积。 在这种结构中，可以更容易地进行FED的体积抽真空。 封闭过程中消除压力积聚的吸气剂可以包含在辅助罐中，并且可以在FED的使用寿命期间保持高真空。
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8.发明授权Bridging centrality: a concept and formula to identify bridging nodes in scale-free networks 失效桥接中心性：确定无大规模网络中的桥接节点的概念和公式公开(公告)号：US07808921B2
公开(公告)日：2010-10-05
申请号：US11804700
申请日：2007-05-18
CPC分类号： H04L45/123 , H04L41/12 , H04L41/145 , H04L41/16
摘要： A method for identifying a bridge node in a network using a processor and memory unit in a specially programmed special purpose-purpose computer including the steps of, for each node in a plurality of nodes in the network: determining a global metric proportional to total traffic flow in the network and through the node; determining a local metric proportional to traffic flow between the node and each second node in the network connected to the node and traffic flow between each second node and each third node in the network connected to a second node; determining a second local metric proportional to the respective traffic flows between each node and each second node; and calculating a respective combination of the global metric and the first and second local metrics; and selecting, a bridge node from among the plurality of nodes based on the respective combinations.
摘要翻译： 一种用于使用专门编程的特殊用途计算机中的处理器和存储器单元来识别网络中的网桥节点的方法，包括以下步骤：对于网络中的多个节点中的每个节点：确定与总流量成比例的全局度量 流经网络并通过节点; 确定与连接到节点的网络中的节点与每个第二节点之间的业务流量成比例的本地度量，以及连接到第二节点的网络中每个第二节点与每个第三节点之间的业务流; 确定与每个节点和每个第二节点之间的相应业务流成比例的第二本地度量; 以及计算所述全局度量和所述第一和第二局部度量的相应组合; 以及基于各个组合从多个节点中选择一个桥接节点。
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公开(公告)号：US06812635B2
公开(公告)日：2004-11-02
申请号：US10179739
申请日：2002-06-24
申请人： Young Rae Cho , Do Hyung Kim , Seong Deok Ahn , Yoon Ho Song , Jin Ho Lee , Kyoung Ik Cho
发明人： Young Rae Cho , Do Hyung Kim , Seong Deok Ahn , Yoon Ho Song , Jin Ho Lee , Kyoung Ik Cho
IPC分类号： H01J162
CPC分类号： H01J1/3048 , H01J9/025 , Y10S977/939
摘要： The present invention relates to a cathode for use in a field emission device. In a triode-type cathode for use in an electron emission device being a core component constituting a field emission device, the present invention includes forming a catalytic layer at the sidewall of a gate hole and then growing an emitter in the catalytic layer, thus uniformly distributing an electric field generated by a voltage applied to a gate electrode over the emitter. Therefore, the present invention can improve the brightness contrast at a low anode voltage and also can control electrons emitted from the emitter only with the gate voltage.
摘要翻译： 本发明涉及用于场发射装置的阴极。 在作为构成场致发射器件的核心部件的电子发射器件中使用的三极管型阴极中，本发明包括在栅极孔的侧壁处形成催化剂层，然后在催化剂层中生长发射极，从而均匀地 分配由施加到发射极上的栅电极的电压产生的电场。 因此，本发明可以提高低阳极电压下的亮度对比度，并且还可以仅利用栅极电压来控制从发射极发射的电子。
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10.发明授权Method for manufacturing semiconductor package containing cylindrical type bump grid array 失效制造包含圆柱形凸块网格阵列的半导体封装的方法公开(公告)号：US06352915B1
公开(公告)日：2002-03-05
申请号：US09680440
申请日：2000-10-06
申请人： Young-rae Cho , Wook-yeol Ryu , Sang-kyun Lee
发明人： Young-rae Cho , Wook-yeol Ryu , Sang-kyun Lee
IPC分类号： H01L2144
CPC分类号： H01L21/4853 , H01L24/73 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/15311 , H05K3/3436 , H05K3/4015 , Y10T29/49144 , Y10T29/49149 , H01L2924/00014 , H01L2924/00012
摘要： A method for manufacturing a semiconductor package comprising the steps of (a) forming a plurality of bumps on a metal frame and a bridge for connecting and supporting the bumps, (b) coating liquid solder on the bumps, (c) aligning the frame with respect to a semiconductor substrate where patterns are formed so that the bumps are positioned on the patterns, (d) soldering the bumps on the patterns, and (e) separating the bumps from the frame by breaking a connecting portion of the bumps and the bridge.
摘要翻译： 一种制造半导体封装的方法，包括以下步骤：（a）在金属框架上形成多个凸块，以及用于连接和支撑凸块的桥，（b）在凸块上涂覆液体焊料，（c）将框架与 相对于形成图案的半导体衬底，使得凸块位于图案上，（d）将凸块焊接在图案上，以及（e）通过破坏凸块和桥的连接部分将凸起与框架分离 。
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