公开(公告)号：US06979584B2

公开(公告)日：2005-12-27

申请号：US10168617

申请日：2000-12-21

申请人： Masayoshi Koike ,  Yuta Tezen ,  Toshio Hiramatsu

发明人： Masayoshi Koike ,  Yuta Tezen ,  Toshio Hiramatsu

IPC分类号： C30B29/38 ,  H01L21/20 ,  H01L21/205 ,  H01L33/06 ,  H01L33/16 ,  H01L33/22 ,  H01L33/32 ,  H01S5/323 ,  H01S5/343

CPC分类号： H01L33/007 ,  B82Y20/00 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/0265 ,  H01L33/0075 ,  H01L33/025 ,  H01S5/34333

摘要： A first Group III nitride compound semiconductor layer 31 is etched, to thereby form an island-like structure such as a dot-like, stripe-shaped, or grid-like structure, so as to provide a trench/post. Thus, a second Group III nitride compound layer 32 can be epitaxially grown, vertically and laterally, from a top surface of the post and a sidewall/sidewalls of the trench serving as a nucleus for epitaxial growth, to thereby bury the trench and also grow the layer in the vertical direction. In this case, propagation of threading dislocations contained in the first Group III nitride compound semiconductor layer 31 can be prevented in the upper portion of the second Group III nitride compound semiconductor 32 that is formed through lateral epitaxial growth. As a result, a region having less threading dislocations is formed at the buried trench.

摘要翻译： 蚀刻第一III族氮化物化合物半导体层31，从而形成诸如点状，条状或栅格状结构的岛状结构，以提供沟槽/柱。 因此，可以从柱的顶表面和用作外延生长的核的沟槽的侧壁/侧壁外延生长第二III族氮化物化合物层32，从而埋入沟槽并且也生长 该层在垂直方向。 在这种情况下，可以通过横向外延生长形成的第二III族氮化物半导体32的上部阻止在第一III族氮化物化合物半导体层31中包含的穿透位错的传播。 结果，在埋入沟槽处形成具有较少穿透位错的区域。

公开(公告)号：US06967122B2

公开(公告)日：2005-11-22

申请号：US10221528

申请日：2001-02-23

申请人： Yuta Tezen

发明人： Yuta Tezen

IPC分类号： H01L21/20 ,  H01L21/205 ,  H01L33/06 ,  H01L33/12 ,  H01L33/32 ,  H01L33/34 ,  H01S5/02 ,  H01S5/323 ,  H01S5/343 ,  H01L21/00

CPC分类号： H01L33/007 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/0265 ,  H01L33/025 ,  H01S5/0213 ,  H01S5/32341 ,  H01S2304/12

摘要： A sapphire substrate 1 is etched so that each trench has a width of 10 μm and a depth of 10 μm were formed at 10 μm of intervals in a stripe pattern. Next, an AlN buffer layer 2 having a thickness of approximately 40 nm is formed mainly on the upper surface and the bottom surface of the trenches of the substrate 1. Then a GaN layer 3 is formed through vertical and lateral epitaxial growth. At this time, lateral epitaxial growth of the buffer layer 21, which was mainly formed on the upper surface of the trenches, filled the trenches and thus establishing a flat top surface. The portions of the GaN layer 3 formed above the top surfaces of the mesas having a depth of 10 μm exhibited significant suppression of threading dislocation in contrast to the portions formed above the bottoms of the trenches.

摘要翻译： 蚀刻蓝宝石衬底1，使得每个沟槽的宽度为10μm，并且以条纹图案以10mum的间隔形成10μm的深度。 接下来，主要在衬底1的沟槽的上表面和底表面上形成厚度约为40nm的AlN缓冲层2。 然后通过垂直和横向外延生长形成GaN层3。 此时，主要形成在沟槽的上表面上的缓冲层21的横向外延生长填充了沟槽，从而建立了平坦的顶表面。 形成在深度为10μm的台面的上表面之上的GaN层3的部分与形成在沟槽的底部上方的部分相反，显着地显示了穿透位错的抑制。

公开(公告)号：US07491984B2

公开(公告)日：2009-02-17

申请号：US10978438

申请日：2004-11-02

申请人： Masayoshi Koike ,  Yuta Tezen ,  Toshio Hiramatsu ,  Seiji Nagai

发明人： Masayoshi Koike ,  Yuta Tezen ,  Toshio Hiramatsu ,  Seiji Nagai

IPC分类号： H01L21/00

CPC分类号： H01L33/007 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/02639 ,  H01L21/02647

摘要： The present invention provides a Group III nitride compound semiconductor with suppressed generation of threading dislocations.A GaN layer 31 is subjected to etching, so as to form an island-like structure having a shape of, for example, dot, stripe, or grid, thereby providing a trench/mesa structure, and a mask 4 is formed at the bottom of the trench such that the upper surface of the mask 4 is positioned below the top surface of the GaN layer 31. A GaN layer 32 is lateral-epitaxially grown with the top surface 31a of the mesa and sidewalls 31b of the trench serving as nuclei, to thereby bury the trench, and then epitaxial growth is effected in the vertical direction. In the upper region of the GaN layer 32 formed above the mask 4 through lateral epitaxial growth, propagation of threading dislocations contained in the GaN layer 31 can be prevented.

摘要翻译： 本发明提供了具有抑制的穿透位错产生的III族氮化物化合物半导体。 对GaN层31进行蚀刻，以形成具有例如点状，条状或格栅形状的岛状结构，由此提供沟槽/台面结构，并且在底部形成掩模4 使得掩模4的上表面位于GaN层31的顶表面之下。GaN层32被侧壁外延生长，台面的顶表面31a和用作核的沟槽的侧壁31b ，从而埋入沟槽，然后在垂直方向进行外延生长。 在通过横向外延生长形成在掩模4上方的GaN层32的上部区域中，可以防止包含在GaN层31中的穿透位错的传播。

公开(公告)号：US07052979B2

公开(公告)日：2006-05-30

申请号：US10467566

申请日：2002-02-12

申请人： Seiji Nagai ,  Kazuyoshi Tomita ,  Shiro Yamazaki ,  Yuta Tezen ,  Toshio Hiramatsu

发明人： Seiji Nagai ,  Kazuyoshi Tomita ,  Shiro Yamazaki ,  Yuta Tezen ,  Toshio Hiramatsu

IPC分类号： H01L21/20

CPC分类号： C30B25/02 ,  C30B25/18 ,  C30B29/403 ,  C30B29/406 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/0265 ,  H01L33/0066 ,  H01L33/007

摘要： When a substrate layer (desired semiconductor crystal) made of a group III nitride compound is grown on a base substrate comprising a lot of projection parts, a cavity in which a semiconductor crystal is not deposited may be formed between each projection part although it depends on conditions such as the size of each projection part, arranging interval between each projection part and crystal growth. So when the thickness of the substrate layer is sufficiently larger compared with the height of the projection part, inner stress or outer stress become easier to act intensively to the projection part. As a result, such stress especially functions as shearing stress toward the projection part. When the shearing stress becomes larger, the projection part is ruptured. So utilizing the shearing stress enables to separate the base substrate and the substrate layer easily. The larger the cavities are formed, the more stress tends to concentrate to the projection parts, to thereby enable to separate the base substrate and the substrate layer more securely.

摘要翻译： 当在包括大量投影部分的基底基板上生长由III族氮化物化合物制成的衬底层（期望的半导体晶体）时，可以在每个突出部分之间形成其中不沉积半导体晶体的空腔，尽管它取决于 条件如每个投影部分的尺寸，每个投影部分之间的间隔和晶体生长。 因此，当基板层的厚度与突出部分的高度相比足够大时，内应力或外应力变得更容易集中于投影部分。 结果，这种应力特别地作用于朝向投影部分的剪切应力。 当剪切应力变大时，突出部分破裂。 因此，利用剪切应力使得能够容易地分离基底和基底层。 形成空穴越大，应力越倾向于集中到突出部分，从而能够更牢固地分离基底基底和基底层。

公开(公告)号：US20060060866A1

公开(公告)日：2006-03-23

申请号：US11222792

申请日：2005-09-12

申请人： Yuta Tezen

发明人： Yuta Tezen

IPC分类号： H01L33/00 ,  H01L31/12 ,  H01L27/15 ,  H01L29/26

CPC分类号： H01L33/007 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/0265 ,  H01L33/025 ,  H01S5/0213 ,  H01S5/32341 ,  H01S2304/12

摘要： A sapphire substrate 1 is etched so that each trench has a width of 10 μm and a depth of 10 μm were formed at 10 μm of intervals in a stripe pattern. Next, an AlN buffer layer 2 having a thickness of approximately 40 nm is formed mainly on the upper surface and the bottom surface of the trenches of the substrate 1. Then a GaN layer 3 is formed through vertical and lateral epitaxial growth. At this time, lateral epitaxial growth of the buffer layer 21, which was mainly formed on the upper surface of the trenches, filled the trenches and thus establishing a flat top surface. The portions of the GaN layer 3 formed above the top surfaces of the mesas having a depth of 10 μm exhibited significant suppression of threading dislocation in contrast to the portions formed above the bottoms of the trenches.

摘要翻译： 蚀刻蓝宝石衬底1，使得每个沟槽的宽度为10μm，并且以条纹图案以10mum的间隔形成10μm的深度。 接下来，主要在衬底1的沟槽的上表面和底表面上形成厚度约为40nm的AlN缓冲层2，然后通过垂直和侧向外延生长形成GaN层3。 此时，主要形成在沟槽的上表面上的缓冲层21的横向外延生长填充了沟槽，从而建立了平坦的顶表面。 形成在深度为10μm的台面的上表面之上的GaN层3的部分与形成在沟槽的底部上方的部分相反，显着地显示了穿透位错的抑制。

公开(公告)号：US07560725B2

公开(公告)日：2009-07-14

申请号：US11226433

申请日：2005-09-15

申请人： Masayoshi Koike ,  Yuta Tezen ,  Toshio Hiramatsu

发明人： Masayoshi Koike ,  Yuta Tezen ,  Toshio Hiramatsu

IPC分类号： H01L31/00

CPC分类号： H01L33/007 ,  B82Y20/00 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/0265 ,  H01L33/0075 ,  H01L33/025 ,  H01S5/34333

摘要： A first Group III nitride compound semiconductor layer 31 is etched, to thereby form an island-like structure such as a dot-like, stripe-shaped, or grid-like structure, so as to provide a trench/post. Thus, a second Group III nitride compound layer 32 can be epitaxially grown, vertically and laterally, from a top surface of the post and a sidewall/sidewalls of the trench serving as a nucleus for epitaxial growth, to thereby bury the trench and also grow the layer in the vertical direction. In this case, propagation of threading dislocations contained in the first Group III nitride compound semiconductor layer 31 can be prevented in the upper portion of the second Group III nitride compound semiconductor 32 that is formed through lateral epitaxial growth. As a result, a region having less threading dislocations is formed at the buried trench.

摘要翻译： 蚀刻第一III族氮化物化合物半导体层31，从而形成诸如点状，条状或栅格状结构的岛状结构，以提供沟槽/柱。 因此，可以从柱的顶表面和用作外延生长的核的沟槽的侧壁/侧壁外延生长第二III族氮化物化合物层32，从而埋入沟槽并且也生长 该层在垂直方向。 在这种情况下，可以通过横向外延生长形成的第二III族氮化物半导体32的上部阻止在第一III族氮化物化合物半导体层31中包含的穿透位错的传播。 结果，在埋入沟槽处形成具有较少穿透位错的区域。

公开(公告)号：US20050093099A1

公开(公告)日：2005-05-05

申请号：US10978438

申请日：2004-11-02

申请人： Masayoshi Koike ,  Yuta Tezen ,  Toshio Hiramatsu ,  Seiji Nagai

发明人： Masayoshi Koike ,  Yuta Tezen ,  Toshio Hiramatsu ,  Seiji Nagai

IPC分类号： H01L21/20 ,  H01L21/205 ,  H01L33/00 ,  H01L29/06 ,  C30B1/00 ,  H01L21/36 ,  H01L29/20 ,  H01L31/0304 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L33/007 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/02639 ,  H01L21/02647

摘要： The present invention provides a Group III nitride compound semiconductor with suppressed generation of threading dislocations. A GaN layer 31 is subjected to etching, so as to form an island-like structure having a shape of, for example, dot, stripe, or grid, thereby providing a trench/mesa structure, and a mask 4 is formed at the bottom of the trench such that the upper surface of the mask 4 is positioned below the top surface of the GaN layer 31. A GaN layer 32 is lateral-epitaxially grown with the top surface 31a of the mesa and sidewalls 31b of the trench serving as nuclei, to thereby bury the trench, and then epitaxial growth is effected in the vertical direction. In the upper region of the GaN layer 32 formed above the mask 4 through lateral epitaxial growth, propagation of threading dislocations contained in the GaN layer 31 can be prevented.

摘要翻译： 本发明提供了具有抑制的穿透位错产生的III族氮化物化合物半导体。 对GaN层31进行蚀刻，以形成具有例如点状，条状或格栅形状的岛状结构，由此提供沟槽/台面结构，并且在底部形成掩模4 使得掩模4的上表面位于GaN层31的顶表面下方。 GaN层32与作为核的沟槽的台面的顶面31a和侧壁31b进行横向外延生长，从而埋入沟槽，然后沿垂直方向进行外延生长。 在通过横向外延生长形成在掩模4上方的GaN层32的上部区域中，可以防止包含在GaN层31中的穿透位错的传播。

公开(公告)号：US06855620B2

公开(公告)日：2005-02-15

申请号：US10258546

申请日：2001-03-02

申请人： Masayoshi Koike ,  Seiji Nagai ,  Yuta Tezen

发明人： Masayoshi Koike ,  Seiji Nagai ,  Yuta Tezen

IPC分类号： C30B29/38 ,  H01L21/20 ,  H01L21/205 ,  H01L33/06 ,  H01L33/32 ,  H01S5/323 ,  H01S5/343 ,  H01L21/36 ,  H01L31/0336 ,  H01L31/3028

CPC分类号： H01L21/0254 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/02639 ,  H01L21/0265 ,  H01L33/007 ,  H01L33/0075

摘要： A GaN layer 31 is subjected to etching, so as to form an island-like structure having, for example, a dot, stripe, or grid shape, thereby providing a trench/mesa structure including mesas and trenches whose bottoms sink into the surface of a substrate base 1. Subsequently, a GaN layer 32 is lateral-epitaxially grown with the top surfaces of the mesas and sidewalls of the trenches serving as nuclei, to thereby fill upper portions of the trenches (depressions of the substrate base 1), and then epitaxial growth is effected in the vertical direction. In this case, propagation of threading dislocations contained in the GaN layer 31 can be prevented in the upper portion of the GaN layer 32 that is formed through lateral epitaxial growth. Thereafter, the remaining GaN layer 31 is removed through etching, together with the GaN layer 32 formed atop the GaN layer 31, and subsequently, a GaN layer 33 is lateral-epitaxially grown with the top surfaces of mesas and sidewalls of trenches serving as nuclei, the mesas and trenches being formed of the remaining GaN layer 32, thereby producing a GaN substrate 30 in which threading dislocations are considerably suppressed. When the area of a portion of the GaN layer 31 at which the GaN substrate 30 is in contact with the substrate base 1 is reduced, separation of the GaN substrate 30 from the substrate base 1 is readily attained.

摘要翻译： 对GaN层31进行蚀刻，以形成例如点状，条状或格子状的岛状结构，从而提供包括台面和沟槽的沟槽/台面结构，其底部沉入到 接下来，GaN层32被横向外延生长，台阶的顶表面和沟槽的侧壁用作核，从而填充沟槽的上部（衬底1的凹陷），以及 则在垂直方向进行外延生长。 在这种情况下，在通过横向外延生长形成的GaN层32的上部可以防止包含在GaN层31中的穿透位错的传播。 此后，残留的GaN层31与形成在GaN层31顶上的GaN层32一起通过蚀刻去除，随后，GaN层33被横向外延生长，作为用作核的沟槽的台面和侧壁的顶面 ，台面和沟槽由剩余的GaN层32形成，从而产生显着地抑制穿透位错的GaN衬底30。 当GaN衬底30与衬底基底1接触的部分GaN层31的面积减小时，容易获得GaN衬底30与衬底基底1的分离。

公开(公告)号：US5933443A

公开(公告)日：1999-08-03

申请号：US707532

申请日：1996-09-04

申请人： Masato Mushiage ,  Yuta Tezen ,  Minoru Murayama

发明人： Masato Mushiage ,  Yuta Tezen ,  Minoru Murayama

IPC分类号： H01L33/14 ,  H01L33/30 ,  H01S5/00 ,  H01S5/20 ,  H01S5/22 ,  H01S5/223 ,  H01S5/343 ,  H01S3/19

CPC分类号： B82Y20/00 ,  H01S5/2231 ,  H01S5/34326 ,  H01S5/205 ,  H01S5/2209

摘要： A semiconductor laser including a first conductive type of lower clad layer, active layer, a second conductive type of upper first clad layer, the first conductive type of current blocking layer having a stripe shaped open portion, and the second conductive type of upper second clad layer laminated in order on the first conductive type of GaAs substrate, wherein each portion in contact with the lower clad layer, the active layer, the upper first and second clad layer and at least the upper second clad layer of the current blocking layer is composed of a compound semiconductor to be represented by a formula, in which (Al.sub.x Ga.sub.1-x).sub.y In.sub.1-y P (x is 0

摘要翻译： 一种半导体激光器，包括第一导电类型的下包层，有源层，第二导电型上第一包层，第一导电类型的电流阻挡层具有条形开口部分，以及第二导电类型的上第二包层 层叠在第一导电类型的GaAs衬底上，其中与下包层，有源层，上第一和第二覆层以及当前阻挡层的至少上部第二覆盖层接触的每个部分被组成 的化合物半导体，其中（Al x Ga 1-x）y In 1-y P（x在下和上第一，第二包层中为0

公开(公告)号：US07462867B2

公开(公告)日：2008-12-09

申请号：US11222792

申请日：2005-09-12

申请人： Yuta Tezen

发明人： Yuta Tezen

IPC分类号： H01L29/26 ,  H01L29/20

CPC分类号： H01L33/007 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/0265 ,  H01L33/025 ,  H01S5/0213 ,  H01S5/32341 ,  H01S2304/12

摘要： A sapphire substrate 1 is etched so that each trench has a width of 10 μm and a depth of 10 μm were formed at 10 μm of intervals in a stripe pattern. Next, an AlN buffer layer 2 having a thickness of approximately 40 nm is formed mainly on the upper surface and the bottom surface of the trenches of the substrate 1. Then a GaN layer 3 is formed through vertical and lateral epitaxial growth. At this time, lateral epitaxial growth of the buffer layer 21, which was mainly formed on the upper surface of the trenches, filled the trenches and thus establishing a flat top surface. The portions of the GaN layer 3 formed above the top surfaces of the mesas having a depth of 10 μm exhibited significant suppression of threading dislocation in contrast to the portions formed above the bottoms of the trenches.

摘要翻译： 蚀刻蓝宝石衬底1，使得每个沟槽的宽度为10μm，并且以条纹图案以10mum的间隔形成10μm的深度。 接下来，主要在衬底1的沟槽的上表面和底表面上形成厚度约为40nm的AlN缓冲层2，然后通过垂直和侧向外延生长形成GaN层3。 此时，主要形成在沟槽的上表面上的缓冲层21的横向外延生长填充了沟槽，从而建立了平坦的顶表面。 形成在深度为10μm的台面的上表面之上的GaN层3的部分与形成在沟槽的底部上方的部分相反，显着地显示了穿透位错的抑制。