-
公开(公告)号：US20140189224A1
公开(公告)日：2014-07-03
申请号：US13728581
申请日：2012-12-27
IPC分类号： G11C7/10
CPC分类号： G11C7/1072 , G11C7/1063 , G11C7/20 , G11C11/4072 , G11C29/023 , G11C29/028 , G11C2207/105 , G11C2207/2254
摘要： Data pin mapping and delay training techniques. Valid values are detected on a command/address (CA) bus at a memory device. A first part of the pattern (high phase) is transmitted via a first subset of data pins on the memory device in response to detecting values on the CA bus; a second part of the pattern (low phase) is transmitted via a second subset of data pins on the memory device in response to detecting values on the CA bus. Signals are sampled at the memory controller from the data pins while the CA pattern is being transmitted to obtain a first memory device's sample (high phase) and the second memory device's sample (low phase) by analyzing the first and the second subset of sampled data pins. The analysis combined with the knowledge of the transmitted pattern on the CA bus leads to finding the unknown data pins mapping. Varying the transmitted CA patterns and the resulting feedbacks sampled on memory controller data signals allows CA/CTRL/CLK signals delay training with and without priory data pins mapping knowledge.
摘要翻译： 数据引脚映射和延迟训练技术。 在存储设备的命令/地址（CA）总线上检测到有效值。 响应于CA总线上的检测值，该模式的第一部分（高相位）经由存储器件上的数据引脚的第一子集传输; 响应于CA总线上的检测值，经由数据引脚的第二子集在存储器件上传送图案（低相位）的第二部分。 信号在存储器控制器处被从数据引脚采样，同时正在发送CA模式，以通过分析采样数据的第一和第二子集来获得第一存储器件的采样（高相位）和第二存储器件的采样（低相位） 针脚。 分析结合CA总线上传输模式的知识，找到未知的数据引脚映射。 改变传输的CA模式和在存储器控制器数据信号上采样的结果反馈允许CA / CTRL / CLK信号延迟训练，并且不使用二进制数据引脚映射知识。
-
公开(公告)号：US20110161752A1
公开(公告)日：2011-06-30
申请号：US12651252
申请日：2009-12-31
申请人： BRYAN L. SPRY , THEODORE Z. SCHOENBORN , PHILIP ABRAHAM , CHRISTOPHER P. MOZAK , DAVID G. ELLIS , JAY J. NEJEDLO , BRUCE QUERBACH , ZVIKA GREENFIELD , RONY GHATTAS , JAYASEKHAR THOLIYIL , CHARLES D. LUCAS , CHRISTOPHER E. YUNKER
发明人： BRYAN L. SPRY , THEODORE Z. SCHOENBORN , PHILIP ABRAHAM , CHRISTOPHER P. MOZAK , DAVID G. ELLIS , JAY J. NEJEDLO , BRUCE QUERBACH , ZVIKA GREENFIELD , RONY GHATTAS , JAYASEKHAR THOLIYIL , CHARLES D. LUCAS , CHRISTOPHER E. YUNKER
摘要： REUT (Robust Electrical Unified Testing) for memory links is introduced which speeds testing, tool development, and debug. In addition it provides training hooks that have enough performance to be used by BIOS to train parameters and conditions that have not been possible with past implementations. Address pattern generation circuitry is also disclosed.
摘要翻译： 引入了用于存储器链接的REUT（鲁棒电气统一测试），可以加速测试，开发和调试。 此外，它还提供了具有足够性能的训练钩子，以供BIOS使用，以训练过去实施中不可能的参数和条件。 还公开了地址图案生成电路。
-
公开(公告)号：US20140157055A1
公开(公告)日：2014-06-05
申请号：US13706196
申请日：2012-12-05
申请人： CHRISTOPHER P. MOZAK , Thoedore Z. Schoenborn , James M. Shehadi , David G. Ellis , Tomer Levy , Zvika Greenfield
发明人： CHRISTOPHER P. MOZAK , Thoedore Z. Schoenborn , James M. Shehadi , David G. Ellis , Tomer Levy , Zvika Greenfield
IPC分类号： G06F11/263
CPC分类号： G06F11/263 , G11C29/02 , G11C29/025 , G11C29/06 , G11C29/52
摘要： A memory subsystem includes logic buffer coupled to a command bus between a memory controller and a memory device. The logic buffer detects that the memory controller places the command bus in a state where the memory controller does not drive the command bus with a valid executable memory device command. In response to detecting the state of the command bus, the logic buffer generates a signal pattern and injects the signal pattern on the command bus after a scheduler of the memory controller to drive the command bus with the signal pattern.
摘要翻译： 存储器子系统包括耦合到存储器控制器和存储器件之间的命令总线的逻辑缓冲器。 逻辑缓冲区检测到存储器控制器将命令总线置于存储器控制器不使用有效的可执行存储器设备命令驱动命令总线的状态。 响应于检测到命令总线的状态，逻辑缓冲器产生信号模式，并且在存储器控制器的调度器之后在命令总线上注入信号模式以用信号模式驱动命令总线。
-
公开(公告)号：US20140089705A1
公开(公告)日：2014-03-27
申请号：US13629008
申请日：2012-09-27
申请人： XIUTING C. MAN , CHRISTOPHER P. MOZAK , SHAUN M. CONRAD , JEFFERY L. KRIEGER , PHILIP R. LEHWALDER , INDER M. SODHI
发明人： XIUTING C. MAN , CHRISTOPHER P. MOZAK , SHAUN M. CONRAD , JEFFERY L. KRIEGER , PHILIP R. LEHWALDER , INDER M. SODHI
IPC分类号： G06F1/32
CPC分类号： G06F1/3296 , G06F1/3275 , G06F1/3287 , Y02D10/14 , Y02D10/171 , Y02D50/20
摘要： Power gating control architectures. A memory device having at least a memory array and input/output (I/O) lines terminated on the memory device with termination circuitry coupled to receive a termination supply voltage (Vtt) with power gating circuitry to selectively gate the termination supply voltage in response to a power gating control signal (VttControl) is coupled with a processing core coupled with the memory device, the processing core to selectively assert and deassert the VttControl signal.
摘要翻译： 电力门控控制架构。 存储器件具有至少存储器阵列和终端于存储器件上的输入/输出（I / O）线，其中终端电路被耦合以用电源门控电路接收终端电源电压（Vtt），以响应于选择性地对终端电源电压进行选通 电力门控控制信号（VttControl）与与存储器件耦合的处理核心耦合，处理核心选择性地断言和解除VttControl信号。
-
5.发明申请SUPPRESSING POWER SUPPLY NOISE USING DATA SCRAMBLING IN DOUBLE DATA RATE MEMORY SYSTEMS 有权使用双重数据速率记忆系统中的数据扫描来抑制电源噪声公开(公告)号：US20090086972A1
公开(公告)日：2009-04-02
申请号：US11864141
申请日：2007-09-28
申请人： CHRISTOPHER P. MOZAK
发明人： CHRISTOPHER P. MOZAK
IPC分类号： H04K1/00
CPC分类号： G06F7/584 , G06F2207/582
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for suppressing power supply noise using data scrambling in double data rate memory systems. In some embodiments, an integrated circuit includes a transmit data path to transmit data to one or more memory devices. The transmit data path may include scrambling logic to generate, in parallel, N pseudo random outputs that are uncorrelated with each other. The output data and the pseudo random outputs are input to XOR logic. The transmit data path transmits the output the of XOR logic which has a substantially white frequency spectrum. Other embodiments are described and claimed.
摘要翻译： 本发明的实施例一般涉及使用双倍数据速率存储器系统中的数据加扰来抑制电源噪声的系统，方法和装置。 在一些实施例中，集成电路包括用于将数据发送到一个或多个存储器设备的发送数据路径。 发送数据路径可以包括加扰逻辑，以并行地生成与彼此不相关的N个伪随机输出。 输出数据和伪随机输出被输入到异或逻辑。 发送数据路径发送具有基本为白色频谱的XOR逻辑的输出。 描述和要求保护其他实施例。
-
公开(公告)号：US20140189433A1
公开(公告)日：2014-07-03
申请号：US13730429
申请日：2012-12-28
IPC分类号： G06F11/07
CPC分类号： G11C29/50 , G11C29/06 , G11C2029/5002
摘要： A memory subsystem can test a memory device in situ, testing the performance of parameters of operation the device in the system it is built into during production. Thus, the system can detect the specific values that will work for one or more operating parameters for the memory device in actual runtime. A test component embedded in the memory subsystem can perform a stress test and identify specific bits or lines of memory that experience failure under one or more stresses. The system can then map out the failed bits or lines to prevent the bits/lines from being used in runtime of the system.
摘要翻译： 存储器子系统可以原位测试存储器件，测试在生产过程中内置的系统中的器件操作参数的性能。 因此，系统可以在实际的运行时间内检测可用于存储器件的一个或多个操作参数的特定值。 嵌入在存储器子系统中的测试组件可以执行压力测试并识别在一个或多个应力下经历故障的特定位或存储器行。 然后，系统可以映射失败的位或行，以防止在系统运行时使用位/线。
-
公开(公告)号：US20140157053A1
公开(公告)日：2014-06-05
申请号：US13706177
申请日：2012-12-05
IPC分类号： G11C29/10
CPC分类号： G11C29/02 , G11C29/022 , G11C29/06 , G11C29/36 , G11C29/50012 , G11C29/52
摘要： A memory subsystem includes a test signal generator of a memory controller that generates a test data signal in response to the memory controller receiving a test transaction. The test transaction indicates one or more I/O operations to perform on an associated memory device. The test signal generator can generate data signals from various different pattern generators. The memory controller scheduler schedules the test data signal pattern, and sends it to the memory device. The memory device can then execute I/O operation(s) to implement the test transaction. The memory controller can read back data written to a specific address of the memory device and compare the read back data with expected data. When the read back data and the expected data do not match, the memory controller can record an error. The error can include the specific address of the error, the specific data, and/or encoded data.
摘要翻译： 存储器子系统包括存储器控制器的测试信号发生器，其响应于存储器控制器接收测试事务而产生测试数据信号。 测试事务指示在相关联的存储设备上执行的一个或多个I / O操作。 测试信号发生器可以从各种不同的模式发生器产生数据信号。 存储器控制器调度器调度测试数据信号模式，并将其发送到存储器件。 然后，存储器件可以执行I / O操作来实现测试事务。 存储器控制器可以读取写入存储器件的特定地址的数据，并将回读数据与预期数据进行比较。 当回读数据和预期数据不匹配时，存储器控制器可以记录错误。 该错误可以包括错误的具体地址，特定数据和/或编码数据。
-
公开(公告)号：US20140140146A1
公开(公告)日：2014-05-22
申请号：US13680604
申请日：2012-11-19
CPC分类号： G05F1/10 , G11C5/145 , G11C5/147 , G11C11/4074 , G11C2207/105 , H02M3/07 , H02M2003/1566
摘要： Circuitry to provide a supply voltage. A voltage regulator is coupled to receive a target reference signal. The voltage regulator generates a supply voltage (Vtt) and is coupled to receive the supply voltage as an input signal. An upper limit comparator receives an upper limit voltage signal that is higher than the target reference voltage signal and the supply voltage to generate a “too high” signal when the supply voltage exceeds an upper threshold. A lower limit comparator receives a lower limit voltage signal that is lower than the target reference voltage signal and the supply voltage to generate a “too low” signal when the supply voltage is below a lower threshold. A pull up current source is coupled to pull the supply voltage up in response to the too low signal. A pull down current source is coupled to pull the supply voltage down in response to the too high signal.
摘要翻译： 电路提供电源电压。 电压调节器被耦合以接收目标参考信号。 电压调节器产生电源电压（Vtt）并被耦合以接收电源电压作为输入信号。 当电源电压超过上限阈值时，上限比较器接收高于目标参考电压信号和电源电压的上限电压信号，以产生“过高”信号。 下限比较器接收低于目标参考电压信号的下限电压信号和电源电压，以在电源电压低于下阈值时产生“太低”信号。 耦合上拉电流源以响应于太低的信号将电源电压拉高。 耦合下拉电流源以响应于太高的信号而拉低电源电压。
-
公开(公告)号：US20150003574A1
公开(公告)日：2015-01-01
申请号：US14038537
申请日：2013-09-26
申请人： CHRISTOPHER P. MOZAK
发明人： CHRISTOPHER P. MOZAK
IPC分类号： H04L7/00
CPC分类号： G06F1/04 , G06F13/4291 , G11C7/222 , G11C27/02 , H03L7/00 , H04L7/0008
摘要： A device with an I/O interface includes a replica clock distribution path matched to a clock distribution path of an unmatched receiver circuit. The device can monitor changes in delay in the replica path, and adjust delay in the real clock distribution path in response to the delay changes detected in the replica path. The receiver circuit includes a data path and a clock distribution network in an unmatched configuration. A ring oscillator circuit includes a replica clock distribution network matched to the real clock distribution network. Thus, delay changes detected for the replica clock distribution network indicates a change in delay in the real clock distribution network, which can be compensated accordingly.
摘要翻译： 具有I / O接口的设备包括与不匹配的接收机电路的时钟分配路径匹配的副本时钟分配路径。 设备可以监视复制路径中延迟的变化，并根据复制路径中检测到的延迟变化来调整实时时钟分配路径中的延迟。 接收机电路包括数据路径和具有不匹配配置的时钟分配网络。 环形振荡器电路包括与真实时钟分配网络匹配的复制时钟分配网络。 因此，对于复制时钟分配网络检测到的延迟改变指示实时时钟分配网络中的延迟变化，这可以相应地进行补偿。
-
公开(公告)号：US20150002408A1
公开(公告)日：2015-01-01
申请号：US13931604
申请日：2013-06-28
CPC分类号： H02M3/158 , G11C7/1057 , G11C29/022 , G11C29/025 , G11C29/028 , G11C2207/105 , H04L25/0276 , H04L25/029
摘要： A transmission line interface circuit includes a voltage regulator to control a voltage swing of the transmission line interface circuit for signal transmission. The transmission line interface circuit includes complementary driver elements, including a p-type driver element to pull up the transmission line in response to a logic high, and an n-type driver element to pull down the transmission line in response to a logic low. The voltage regulator is coupled between one of the driver elements and a respective voltage reference to reduce a voltage swing of the transmission line interface circuit.
摘要翻译： 传输线接口电路包括用于控制用于信号传输的传输线接口电路的电压摆幅的电压调节器。 传输线接口电路包括互补驱动器元件，包括响应于逻辑高来上拉传输线的p型驱动器元件，以及响应于逻辑低来拉低传输线的n型驱动器元件。 电压调节器耦合在驱动器元件之一和相应的电压基准之间，以减小传输线接口电路的电压摆幅。
-
-
-
-
-
-
-
-
-
搜索结果
10 条记录 (耗时 0.022 秒)
