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    SYSTEMS AND METHODS FOR PURGING REACTOR LOWER CHAMBERS WITH ETCHANTS DURING FILM DEPOSITION
    1.
    发明申请
    SYSTEMS AND METHODS FOR PURGING REACTOR LOWER CHAMBERS WITH ETCHANTS DURING FILM DEPOSITION 有权

    公开(公告)号：US20230116427A1

    公开(公告)日：2023-04-13

    申请号：US17962009

    申请日：2022-10-07

    Applicant: ASM IP Holding B.V.

    Inventor： Junwei Su ,  Jiwen Xiang ,  Shujin Huang ,  Loc Vinh Tran ,  Wentao Wang ,  Xing Lin

    IPC: C23C16/44 ,  H01L21/687 ,  H01L21/02 ,  C23C16/52 ,  C23C16/02 ,  C23C16/24

    Abstract: A semiconductor processing system includes a gas delivery module, and a chamber body connected to the gas delivery module. The divider has an aperture, is fixed within an interior of the chamber body, and separates an interior of the chamber body into upper and lower chambers, the aperture fluidly coupling the lower chamber to the upper chamber. A susceptor is arranged within the aperture. A controller is operably connected to the gas delivery module to purge the lower chamber with a first purge flow including an etchant while etching the upper chamber, purge the lower chamber with a second purge flow including the etchant while depositing a precoat in the upper chamber, and purge the lower chamber with a third purge flow including the etchant while depositing a film onto a substrate in the upper chamber. Film deposition methods and lower chamber etchant purge kits are also described.

    WAFER FAR EDGE TEMPERATURE MEASUREMENT SYSTEM WITH LAMP BANK ALIGNMENT
    2.
    发明申请
    WAFER FAR EDGE TEMPERATURE MEASUREMENT SYSTEM WITH LAMP BANK ALIGNMENT 有权

    公开(公告)号：US20220301906A1

    公开(公告)日：2022-09-22

    申请号：US17697164

    申请日：2022-03-17

    Applicant: ASM IP Holding B.V.

    Inventor： Rutvij Naik ,  Shujin Huang ,  Junwei Su ,  Xing Lin

    IPC: H01L21/67 ,  H05B31/00

    Abstract: A reactor system designed to provide accurate monitoring of wafer temperatures during deposition steps. The reactor system includes a pyrometer mounting assembly supporting and positioning three or more pyrometers (e.g., infrared (IR) pyrometers) relative to the reaction chamber to measure a center wafer temperature and an edge wafer temperature as well as reaction chamber temperature. The pyrometer mounting assembly provides a small spot size or temperature sensing area with the edge pyrometer to accurately measure edge wafer temperatures. A jig assembly, and installation method for each tool setup, is provided for use in achieving accurate alignment of the IR pyrometer sensing spot (and the edge pyrometer) relative to the wafer, when the pyrometer mounting assembly is mounted upon a lamp bank in the reactor system or in tool setup. The wafer edge temperature sensing with the reactor system assembled with proper alignment ensures accurate and repeatable measurement of wafer temperatures.

    LIFT PIN ACTUATORS FOR SEMICONDUCTOR PROCESSING SYSTEMS AND RELATED METHODS
    5.
    发明公开
    LIFT PIN ACTUATORS FOR SEMICONDUCTOR PROCESSING SYSTEMS AND RELATED METHODS 审中-公开

    公开(公告)号：US20240112946A1

    公开(公告)日：2024-04-04

    申请号：US18476067

    申请日：2023-09-27

    Applicant: ASM IP Holding, B.V.

    Inventor： Bradley Wayne Evans ,  Shujin Huang ,  Junwei Su ,  Loc Tran ,  Xing Lin ,  Alexandros Demos

    IPC: H01L21/687 ,  C23C16/458

    CPC classification number: H01L21/68742 ,  C23C16/4585

    Abstract: A lift pin actuator includes a castellated annulus, a first arm, a second arm, and a pin pad. The annulus arranged along a rotation axis and has a first merlon and a second merlon circumferentially separated by a crenel. The first arm is connected to the first merlon and extends outward from the annulus, the second arm is connected to the second merlon and extends outward from the annulus, and the second arm is circumferentially spaced from the first arm by a radial gap. The pin pad is connected to the annulus by the first arm and the second arm, is radially spaced from the annulus by the radial gap, and radially overlaps the crenel to nest a support member within the lift pin actuator during translation of the lift pin actuator along the rotation axis relative to the support member. Process kits, semiconductor processing systems, methods of making lift pin actuators and related material layer deposition methods are also described.

    SUBSTRATE SUPPORTS FOR SEMICONDUCTOR PROCESSING SYSTEMS
    6.
    发明申请
    SUBSTRATE SUPPORTS FOR SEMICONDUCTOR PROCESSING SYSTEMS 有权

    公开(公告)号：US20230128390A1

    公开(公告)日：2023-04-27

    申请号：US18048099

    申请日：2022-10-20

    Applicant: ASM IP Holding, B.V.

    Inventor： Shujin Huang ,  Junweli Su ,  Wentao Wang ,  Zhizhong Chen ,  Xing Lin ,  Jiwen Xiang

    IPC: H01L21/687

    Abstract: A substrate support includes a disc body with an upper surface and an opposite lower surface arranged along a rotation axis. The upper surface has a circular concave portion extending about the rotation axis, an annular ledge portion extending circumferentially about the concave portion, and an annular rim portion extending circumferentially about the ledge portion connecting to the concave portion of the disc body by the ledge portion of the disc body. The ledge portion slopes downward radially outward from the rotation axis to seat a substrate on the disc body such that a beveled edge of the substrate is cantilevered above the ledge portion of the upper surface of the disc body. Substrate support assemblies, semiconductor processing systems, and film deposition methods are also described.

    Susceptor
    7.
    外观设计
    Susceptor 有权

    公开(公告)号：USD1030687S1

    公开(公告)日：2024-06-11

    申请号：US29840698

    申请日：2022-05-31

    Applicant: ASM IP Holding B.V.

    Designer： Shujin Huang ,  Junwei Su ,  Wentao Wang ,  Xing Lin

    Abstract: FIG. 1 is a front perspective view of a susceptor, showing our new design;
    FIG. 2 is a bottom perspective view thereof;
    FIG. 3 is right side view thereof;
    FIG. 4 is a left side view thereof;
    FIG. 5 is front view thereof;
    FIG. 6 is back view thereof;
    FIG. 7 is a top view thereof; and,
    FIG. 8 is a bottom view thereof.

    SUBSTRATE SUPPORTS, SEMICONDUCTOR PROCESSING SYSTEMS, AND MATERIAL LAYER DEPOSITION METHODS
    8.
    发明公开
    SUBSTRATE SUPPORTS, SEMICONDUCTOR PROCESSING SYSTEMS, AND MATERIAL LAYER DEPOSITION METHODS 审中-公开

    公开(公告)号：US20230386874A1

    公开(公告)日：2023-11-30

    申请号：US18324411

    申请日：2023-05-26

    Applicant: ASM IP Holding, B.V.

    Inventor： Shujin Huang ,  Junwei Su ,  Wentao Wang ,  Xing Lin

    IPC: H01L21/673 ,  H01L21/687 ,  H01L21/02 ,  H01L21/3213

    CPC classification number: H01L21/67316 ,  H01L21/68742 ,  H01L21/02293 ,  H01L21/3213

    Abstract: A substrate support includes a disc body with upper and lower surfaces spaced apart by a thickness. The upper surface has a circular concavity extending about a rotation axis, an annular ledge portion radially outward of the concavity extending circumferentially about the concavity, and an annular rim portion radially outward of the ledge portion extending circumferentially about the ledge portion. The concavity has a circular perforated portion and an annular unperforated portion. The perforated portion extends about the rotation axis and defines two or more perforations to issue an etchant into a cavity defined between the concavity and a backside of a substrate seated on the substrate support. The unperforated portion is radially outward of the perforated portion and extends circumferentially about the perforated portion to limit etching of the backside of the substrate by the etchant. Semiconductor processing systems and material layer deposition methods are also described.

    EPITAXY FAST RAMP TEMPERATURE CONTROL SYSTEMS AND PROCESSES
    10.
    发明申请
    EPITAXY FAST RAMP TEMPERATURE CONTROL SYSTEMS AND PROCESSES 有权

    公开(公告)号：US20240404891A1

    公开(公告)日：2024-12-05

    申请号：US18677160

    申请日：2024-05-29

    Applicant: ASM IP Holding B.V.

    Inventor： Junwei Su ,  Shujin Huang ,  Kevin Eugene Quinn ,  Yang Wang ,  Zhizhong Chen ,  Chengzi Huang

    IPC: H01L21/66 ,  H01L21/324

    Abstract: Substrate processing systems and methods include: (a) seating a substrate on a support; (b) optically measuring center substrate temperature using a first pyrometer; (c) optically measuring edge substrate temperature using a second pyrometer; and (d) determining an edge offset temperature between the edge substrate temperature and the center substrate temperature. Three temperature ramping steps are used to heat up the substrate for processing: two fast ramping steps and one slow ramping steps. After substrate processing, an initial, controlled cooling step is provided. During at least the second fast temperature ramping step, the slow temperature ramping step, the substrate processing step(s), and the initial controlled cooling step, heating of the substrate is controlled to place and/or hold the edge offset temperature within predetermined ranges in order to maintain uniform temperature and/or a desired temperature gradient across the substrate. Such systems and methods help avoid crystal defects (e.g., slip) and/or auto-doping.

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