公开(公告)号：US09397186B2

公开(公告)日：2016-07-19

申请号：US14602125

申请日：2015-01-21

Applicant: Avogy, Inc.

Inventor： Madhan M. Raj ,  Brian Alvarez ,  David P. Bour ,  Andrew P. Edwards ,  Hui Nie ,  Isik C. Kizilyalli

IPC: H01L21/328 ,  H01L21/329 ,  H01L29/868 ,  H01L29/872 ,  H01L29/66 ,  H01L29/06 ,  H01L29/20 ,  H01L21/02

CPC classification number: H01L29/66143 ,  H01L21/0254 ,  H01L21/02664 ,  H01L29/0619 ,  H01L29/2003 ,  H01L29/66121 ,  H01L29/66212 ,  H01L29/872

Abstract: An MPS diode includes a III-nitride substrate characterized by a first conductivity type and a first dopant concentration and having a first side and a second side. The MPS diode also includes a III-nitride epitaxial structure comprising a first III-nitride epitaxial layer coupled to the first side of the substrate, wherein a region of the first III-nitride epitaxial layer comprises an array of protrusions. The III-nitride epitaxial structure also includes a plurality of III-nitride regions of a second conductivity type, each partially disposed between adjacent protrusions. Each of the plurality of III-nitride regions of the second conductivity type comprises a first section laterally positioned between adjacent protrusions and a second section extending in a direction normal to the first side of the substrate. The MPS diode further includes a first metallic structure electrically coupled to one or more of the protrusions and to one or more of the second sections.

Abstract translation: MPS二极管包括以第一导电类型和第一掺杂剂浓度为特征的III族氮化物衬底，其具有第一侧和第二侧。 MPS二极管还包括III族氮化物外延结构，其包括耦合到衬底的第一侧的第一III族氮化物外延层，其中第一III族氮化物外延层的区域包括突起阵列。 III族氮化物外延结构还包括多个第二导电类型的III族氮化物区域，每个部分设置在相邻的突起之间。 第二导电类型的多个III族氮化物区域中的每一个包括横向位于相邻突起之间的第一部分和沿着垂直于衬底的第一侧的方向延伸的第二部分。 MPS二极管还包括电耦合到一个或多个突起和一个或多个第二部分的第一金属结构。

公开(公告)号：US09269793B2

公开(公告)日：2016-02-23

申请号：US14489761

申请日：2014-09-18

Applicant: Avogy, Inc.

Inventor： Richard J. Brown ,  Isik C. Kizilyalli ,  Hui Nie ,  Andrew P. Edwards ,  David P. Bour

IPC: H01L29/20 ,  H01L21/20 ,  H01L21/332 ,  H01L29/66 ,  H01L29/812 ,  H01L29/808 ,  H01L21/02 ,  H01L21/32 ,  H01L29/36 ,  H01L29/47 ,  H01L29/10 ,  H01L29/16

CPC classification number: H01L29/66856 ,  H01L21/0254 ,  H01L21/02647 ,  H01L21/32 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/475 ,  H01L29/8083 ,  H01L29/812 ,  H01L29/8122

Abstract: A semiconductor structure includes a III-nitride substrate and a drift region coupled to the III-nitride substrate along a growth direction. The semiconductor substrate also includes a channel region coupled to the drift region. The channel region is defined by a channel sidewall disposed substantially along the growth direction. The semiconductor substrate further includes a gate region disposed laterally with respect to the channel region.

Abstract translation: 半导体结构包括III族氮化物衬底和沿生长方向耦合到III族氮化物衬底的漂移区域。 半导体衬底还包括耦合到漂移区的沟道区。 通道区域由基本沿着生长方向设置的通道侧壁限定。 半导体衬底还包括相对于沟道区域侧向设置的栅极区域。

公开(公告)号：US20150243758A1

公开(公告)日：2015-08-27

申请号：US14711547

申请日：2015-05-13

Applicant: AVOGY, Inc.

Inventor： Hui Nie ,  Andrew P. Edwards ,  Isik Kizilyalli ,  David P. Bour ,  Thomas R. Prunty ,  Quentin Diduck

IPC: H01L29/66 ,  H01L29/201 ,  H01L29/06 ,  H01L29/808 ,  H01L21/02 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L29/66462 ,  H01L21/02389 ,  H01L21/0254 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/122 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/66431 ,  H01L29/66909 ,  H01L29/66924 ,  H01L29/8083

Abstract: A vertical JFET includes a GaN substrate comprising a drain of the JFET and a plurality of patterned epitaxial layers coupled to the GaN substrate. A distal epitaxial layer comprises a first part of a source channel and adjacent patterned epitaxial layers are separated by a gap having a predetermined distance. The vertical JFET also includes a plurality of regrown epitaxial layers coupled to the distal epitaxial layer and disposed in at least a portion of the gap. A proximal regrown epitaxial layer comprises a second part of the source channel. The vertical JFET further includes a source contact passing through portions of a distal regrown epitaxial layer and in electrical contact with the source channel, a gate contact in electrical contact with a distal regrown epitaxial layer, and a drain contact in electrical contact with the GaN substrate.

Abstract translation: 垂直JFET包括包括JFET的漏极和耦合到GaN衬底的多个图案化外延层的GaN衬底。 远端外延层包括源通道的第一部分，并且相邻的图案化外延层被具有预定距离的间隙分开。 垂直JFET还包括耦合到远端外延层并且设置在间隙的至少一部分中的多个再生长的外延层。 近端再生长的外延层包括源通道的第二部分。 垂直JFET还包括通过远端再生长外延层的部分并与源极沟道电接触的源极接触，与远端再生长的外延层电接触的栅极接触，以及与GaN衬底电接触的漏极接触 。

公开(公告)号：US20150200097A1

公开(公告)日：2015-07-16

申请号：US14558393

申请日：2014-12-02

Applicant: Avogy, Inc.

Inventor： Isik C. Kizilyalli ,  Hui Nie ,  Andrew P. Edwards ,  Linda Romano ,  David P. Bour ,  Richard J. Brown ,  Thomas R. Prunty

IPC: H01L21/265 ,  H01L29/06 ,  H01L29/66 ,  H01L29/20

CPC classification number: H01L21/2654 ,  H01L29/0619 ,  H01L29/0642 ,  H01L29/2003 ,  H01L29/66143 ,  H01L29/6631 ,  H01L29/66446 ,  H01L29/66856 ,  H01L29/8083 ,  H01L29/868 ,  H01L29/872

Abstract: A method of making an edge terminated semiconductor device includes providing a GaN substrate having a GaN epitaxial layer grown thereon and exposing a portion of the GaN epitaxial layer to ion implantation. The energy dose is selected to provide a resistivity that is at least 90% of maximum achievable resistivity. The method also includes depositing a conductive layer over a portion of the implanted region.

Abstract translation: 制造边缘端接的半导体器件的方法包括提供其上生长有GaN外延层的GaN衬底，并将GaN外延层的一部分暴露于离子注入。 选择能量剂量以提供至少达到最大可实现电阻率的90％的电阻率。 该方法还包括在植入区域的一部分上沉积导电层。

公开(公告)号：US20150140746A1

公开(公告)日：2015-05-21

申请号：US14574265

申请日：2014-12-17

Applicant: AVOGY, INC.

Inventor： Isik C. Kizilyalli ,  Hui Nie ,  Andrew P. Edwards ,  Linda Romano ,  David P. Bour ,  Richard J. Brown ,  Thomas R. Prunty

IPC: H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/66909 ,  H01L21/823487 ,  H01L27/0605 ,  H01L27/0611 ,  H01L27/0629 ,  H01L27/0727 ,  H01L27/098 ,  H01L29/2003 ,  H01L29/66143 ,  H01L29/8083 ,  H01L29/872

Abstract: An integrated device including a vertical III-nitride FET and a Schottky diode includes a drain comprising a first III-nitride material, a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction, and a channel region comprising a third III-nitride material coupled to the drift region. The integrated device also includes a gate region at least partially surrounding the channel region, a source coupled to the channel region, and a Schottky contact coupled to the drift region. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride FET and the Schottky diode is along the vertical direction.

Abstract translation: 包括垂直III族氮化物FET和肖特基二极管的集成器件包括：包括第一III族氮化物材料的漏极，包括耦合到漏极并沿垂直方向邻近漏极设置的第二III族氮化物材料的漂移区， 以及包括耦合到所述漂移区的第三III族氮化物材料的沟道区。 集成器件还包括至少部分地围绕沟道区的栅极区域，耦合到沟道区的源极和耦合到漂移区域的肖特基接触。 沟道区域沿着垂直方向设置在漏极和源极之间，使得垂直III族氮化物FET和肖特基二极管的工作期间的电流沿垂直方向。

公开(公告)号：US20140235030A1

公开(公告)日：2014-08-21

申请号：US14264998

申请日：2014-04-29

Applicant: AVOGY, INC.

Inventor： Donald R. Disney ,  Andrew P. Edwards ,  Hui Nie ,  Richard J. Brown ,  Isik C. Kizilyalli ,  David P. Bour ,  Linda Romano ,  Thomas R. Prunty

IPC: H01L21/761 ,  H01L21/765

CPC classification number: H01L21/761 ,  H01L21/2654 ,  H01L21/266 ,  H01L21/765 ,  H01L29/0619 ,  H01L29/0642 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66136 ,  H01L29/66212 ,  H01L29/6631 ,  H01L29/66909 ,  H01L29/8083 ,  H01L29/872

Abstract: A method for fabricating an edge termination structure includes providing a substrate having a first surface and a second surface and a first conductivity type, forming a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the substrate, and forming a second GaN epitaxial layer of a second conductivity type opposite to the first conductivity type. The second GaN epitaxial layer is coupled to the first GaN epitaxial layer. The method also includes implanting ions into a first region of the second GaN epitaxial layer to electrically isolate a second region of the second GaN epitaxial layer from a third region of the second GaN epitaxial layer. The method further includes forming an active device coupled to the second region of the second GaN epitaxial layer and forming the edge termination structure coupled to the third region of the second GaN epitaxial layer.

Abstract translation: 一种用于制造边缘终端结构的方法包括提供具有第一表面和第二表面和第一导电类型的衬底，形成耦合到衬底的第一表面的第一导电类型的第一GaN外延层，并形成第二 与第一导电类型相反的第二导电类型的GaN外延层。 第二GaN外延层耦合到第一GaN外延层。 该方法还包括将离子注入第二GaN外延层的第一区域以将第二GaN外延层的第二区域与第二GaN外延层的第三区域电隔离。 该方法还包括形成耦合到第二GaN外延层的第二区域并形成耦合到第二GaN外延层的第三区域的边缘端接结构的有源器件。

公开(公告)号：US09171751B2

公开(公告)日：2015-10-27

申请号：US14264998

申请日：2014-04-29

Applicant: AVOGY, INC.

Inventor： Donald R. Disney ,  Andrew P. Edwards ,  Hui Nie ,  Richard J. Brown ,  Isik C. Kizilyalli ,  David P. Bour ,  Linda Romano ,  Thomas R. Prunty

IPC: H01L29/06 ,  H01L21/761 ,  H01L21/266 ,  H01L21/265 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/808 ,  H01L29/872

CPC classification number: H01L21/761 ,  H01L21/2654 ,  H01L21/266 ,  H01L21/765 ,  H01L29/0619 ,  H01L29/0642 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66136 ,  H01L29/66212 ,  H01L29/6631 ,  H01L29/66909 ,  H01L29/8083 ,  H01L29/872

Abstract: A method for fabricating an edge termination structure includes providing a substrate having a first surface and a second surface and a first conductivity type, forming a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the substrate, and forming a second GaN epitaxial layer of a second conductivity type opposite to the first conductivity type. The second GaN epitaxial layer is coupled to the first GaN epitaxial layer. The method also includes implanting ions into a first region of the second GaN epitaxial layer to electrically isolate a second region of the second GaN epitaxial layer from a third region of the second GaN epitaxial layer. The method further includes forming an active device coupled to the second region of the second GaN epitaxial layer and forming the edge termination structure coupled to the third region of the second GaN epitaxial layer.

Abstract translation: 一种用于制造边缘终端结构的方法包括提供具有第一表面和第二表面和第一导电类型的衬底，形成耦合到衬底的第一表面的第一导电类型的第一GaN外延层，并形成第二 与第一导电类型相反的第二导电类型的GaN外延层。 第二GaN外延层耦合到第一GaN外延层。 该方法还包括将离子注入第二GaN外延层的第一区域以将第二GaN外延层的第二区域与第二GaN外延层的第三区域电隔离。 该方法还包括形成耦合到第二GaN外延层的第二区域并形成耦合到第二GaN外延层的第三区域的边缘端接结构的有源器件。

公开(公告)号：US20150179772A1

公开(公告)日：2015-06-25

申请号：US14489761

申请日：2014-09-18

Applicant: Avogy, Inc.

Inventor： Richard J. Brown ,  Isik C. Kizilyalli ,  Hui Nie ,  Andrew P. Edwards ,  David P. Bour

IPC: H01L29/66 ,  H01L21/32 ,  H01L29/47 ,  H01L21/02 ,  H01L29/20 ,  H01L29/36

CPC classification number: H01L29/66856 ,  H01L21/0254 ,  H01L21/02647 ,  H01L21/32 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/475 ,  H01L29/8083 ,  H01L29/812 ,  H01L29/8122

Abstract: A semiconductor structure includes a III-nitride substrate and a drift region coupled to the III-nitride substrate along a growth direction. The semiconductor substrate also includes a channel region coupled to the drift region. The channel region is defined by a channel sidewall disposed substantially along the growth direction. The semiconductor substrate further includes a gate region disposed laterally with respect to the channel region.

Abstract translation: 半导体结构包括III族氮化物衬底和沿生长方向耦合到III族氮化物衬底的漂移区域。 半导体衬底还包括耦合到漂移区的沟道区。 通道区域由基本沿着生长方向设置的通道侧壁限定。 半导体衬底还包括相对于沟道区域侧向设置的栅极区域。

公开(公告)号：US08941117B2

公开(公告)日：2015-01-27

申请号：US13935345

申请日：2013-07-03

Applicant: Avogy, Inc.

Inventor： Isik C. Kizilyalli ,  Hui Nie ,  Andrew P. Edwards ,  Linda Romano ,  David P. Bour ,  Richard J. Brown ,  Thomas R. Prunty

IPC: H01L31/0256 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L29/66 ,  H01L29/808 ,  H01L29/872 ,  H01L29/20 ,  H01L27/06 ,  H01L27/07 ,  H01L27/098

CPC classification number: H01L29/66909 ,  H01L21/823487 ,  H01L27/0605 ,  H01L27/0611 ,  H01L27/0629 ,  H01L27/0727 ,  H01L27/098 ,  H01L29/2003 ,  H01L29/66143 ,  H01L29/8083 ,  H01L29/872

Abstract: An integrated device including a vertical III-nitride FET and a Schottky diode includes a drain comprising a first III-nitride material, a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction, and a channel region comprising a third III-nitride material coupled to the drift region. The integrated device also includes a gate region at least partially surrounding the channel region, a source coupled to the channel region, and a Schottky contact coupled to the drift region. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride FET and the Schottky diode is along the vertical direction.

Abstract translation: 包括垂直III族氮化物FET和肖特基二极管的集成器件包括：包括第一III族氮化物材料的漏极，包括耦合到漏极并沿垂直方向邻近漏极设置的第二III族氮化物材料的漂移区， 以及包括耦合到所述漂移区的第三III族氮化物材料的沟道区。 集成器件还包括至少部分地围绕沟道区的栅极区域，耦合到沟道区的源极和耦合到漂移区域的肖特基接触。 沟道区域沿着垂直方向设置在漏极和源极之间，使得垂直III族氮化物FET和肖特基二极管的工作期间的电流沿垂直方向。

公开(公告)号：US20150017792A1

公开(公告)日：2015-01-15

申请号：US14498916

申请日：2014-09-26

Applicant: Avogy, Inc.

Inventor： David P. Bour ,  Richard J. Brown ,  Isik C. Kizilyalli ,  Thomas R. Prunty ,  Linda Romano ,  Andrew P. Edwards ,  Hui Nie ,  Mahdan Raj

IPC: H01L21/265 ,  H01L21/033 ,  H01L21/324 ,  H01L21/266

CPC classification number: H01L21/26546 ,  H01L21/0332 ,  H01L21/2258 ,  H01L21/266 ,  H01L21/3245 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/872

Abstract: A method of forming a doped region in a III-nitride substrate includes providing the III-nitride substrate and forming a masking layer having a predetermined pattern and coupled to a portion of the III-nitride substrate. The III-nitride substrate is characterized by a first conductivity type and the predetermined pattern defines exposed regions of the III-nitride substrate. The method also includes heating the III-nitride substrate to a predetermined temperature and placing a dual-precursor gas adjacent the exposed regions of the III-nitride substrate. The dual-precursor gas includes a nitrogen source and a dopant source. The method further includes maintaining the predetermined temperature for a predetermined time period, forming p-type III-nitride regions adjacent the exposed regions of the III-nitride substrate, and removing the masking layer.

Abstract translation: 在III族氮化物衬底中形成掺杂区域的方法包括提供III族氮化物衬底并形成具有预定图案并与III族氮化物衬底的一部分耦合的掩模层。 III族氮化物衬底的特征在于第一导电类型，并且预定图案限定III族氮化物衬底的暴露区域。 该方法还包括将III族氮化物衬底加热到​​预定温度，并将双前体气体放置在III族氮化物衬底的暴露区域附近。 双前体气体包括氮源和掺杂剂源。 该方法还包括将预定温度保持预定时间段，形成与III族氮化物衬底的暴露区域相邻的p型III族氮化物区域，以及去除掩模层。