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17 条记录 (耗时 0.025 秒)

    Fault state detection mechanism for a ring-counter-based frequency divider-by-N that generates non-overlapping N-phases of divide-by-N clocks with 1/N duty ratio
    2.
    发明授权
    Fault state detection mechanism for a ring-counter-based frequency divider-by-N that generates non-overlapping N-phases of divide-by-N clocks with 1/N duty ratio 有权
    基于振铃计数器的分频器N的故障状态检测机制，其产生具有1 / N占空比的N分频N倍的非重叠N相

    公开(公告)号：US06950490B1

    公开(公告)日：2005-09-27

    申请号：US10751673

    申请日：2004-01-05

    申请人： Yongseon Koh ,  Jitendra Mohan

    发明人： Yongseon Koh ,  Jitendra Mohan

    IPC分类号： H03K21/40 ,  H03K23/54

    CPC分类号： H03K21/40 ,  H03K23/54

    摘要： A fault state detector for a ring counter is formed from unit current sources each switched under the control of a different one of the outputs of the ring counter. The currents switched in that manner are passed through a unit resistance to generate a voltage signal proportional to the number of asserted outputs from the ring counter. The voltage signal is compared to boundary reference values for valid states of the ring counter outputs and, if the voltage signal is not between the boundary reference values, a fault state is indicated.

    摘要翻译： 环形计数器的故障状态检测器由单个电流源形成，每个电流源在环形计数器的不同输出端的控制下切换。 以这种方式切换的电流通过单位电阻以产生与来自环形计数器的断言输出数量成比例的电压信号。 将电压信号与环形计数器输出的有效状态的边界参考值进行比较，如果电压信号不在边界参考值之间，则指示故障状态。

    Method for generating non-overlapping N-phases of divide-by-N clocks with precise 1/N duty ratio using a shift register
    3.
    发明授权
    Method for generating non-overlapping N-phases of divide-by-N clocks with precise 1/N duty ratio using a shift register 有权
    使用移位寄存器以精确的1 / N占空比产生N个时钟的非重叠N相的方法

    公开(公告)号：US07395286B1

    公开(公告)日：2008-07-01

    申请号：US10751674

    申请日：2004-01-05

    申请人： Yongseon Koh ,  Jitendra Mohan

    发明人： Yongseon Koh ,  Jitendra Mohan

    IPC分类号： G06F7/52 ,  G06F1/02

    CPC分类号： G06F1/06 ,  G06F7/68

    摘要： A divide-by-N clock frequency divider producing N non-overlapping clocks each with precise 1/N duty ratio is implemented by a counter, a token generator and N-bit shift register. Every N clock cycles, a pulse is generated as a token from a logical combination of signals from the counter. The pulse is passed along a shift register having balanced load capacitances under control of the clock edge, ensuring a precise 1/N duty ratio that is unaffected by load capacitances from the fault state detection and/or reset circuitry. In this manner, a higher operating frequency may be achieved with low power consumption.

    摘要翻译： 产生N个具有精确1 / N占空比的非重叠时钟的N分频分频器由计数器，令牌发生器和N位移位寄存器实现。 每N个时钟周期，从来自计数器的信号的逻辑组合产生一个脉冲作为令牌。 在时钟边沿的控制下，脉冲沿着具有平衡负载电容的移位寄存器传递，确保不受故障状态检测和/或复位电路的负载电容影响的精确1 / N占空比。 以这种方式，可以以低功耗实现更高的工作频率。

    System and method for providing a constant swing high-gain complementary differential limiting amplifier
    5.
    发明授权
    System and method for providing a constant swing high-gain complementary differential limiting amplifier 有权
    用于提供恒定摆幅高增益互补差分限幅放大器的系统和方法

    公开(公告)号：US07256651B1

    公开(公告)日：2007-08-14

    申请号：US11034041

    申请日：2005-01-12

    申请人： Ramsin M. Ziazadeh ,  Yongseon Koh

    发明人： Ramsin M. Ziazadeh ,  Yongseon Koh

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45237 ,  H03F3/45183 ,  H03F2200/447 ,  H03F2203/45288 ,  H03F2203/45318 ,  H03F2203/45641 ,  H03F2203/45696

    摘要： A system and a method are disclosed for providing a constant swing high-gain complementary differential limiting amplifier. High gain for the differential amplifier is created by providing a current to the driving transistors that is a combination of any of (a) constant current, (b) transconductance based current, and (c) temperature compensated based current. A constant differential output swing is created by providing a varying differential current to the output load resistors of the differential amplifier that tracks process and temperature variations within the output load resistors.

    摘要翻译： 公开了用于提供恒定摆幅高增益互补差分限幅放大器的系统和方法。 差分放大器的高增益是通过向（a）恒定电流，（b）基于跨导的电流和（c）基于温度补偿的电流）中的任何一个的组合的驱动晶体管提供电流而产生的。 通过向差分放大器的输出负载电阻器提供变化的差分电流来产生恒定的差分输出摆幅，该差分放大器跟踪输出负载电阻器内的过程和温度变化。

    Optical sub-assembly for opto-electronic modules
    6.
    发明申请
    Optical sub-assembly for opto-electronic modules 有权
    光电子模块的光学子组件

    公开(公告)号：US20050175297A1

    公开(公告)日：2005-08-11

    申请号：US11095637

    申请日：2005-03-30

    申请人： William Mazotti ,  Peter Deane ,  Luu Nguyen ,  Ken Pham ,  Bruce Roberts ,  Jia Liu ,  Yongseon Koh ,  John Briant ,  Roger Clarke ,  Michael Nelson ,  Christopher Smith ,  Janet Townsend

    发明人： William Mazotti ,  Peter Deane ,  Luu Nguyen ,  Ken Pham ,  Bruce Roberts ,  Jia Liu ,  Yongseon Koh ,  John Briant ,  Roger Clarke ,  Michael Nelson ,  Christopher Smith ,  Janet Townsend

    IPC分类号： G02B6/42 ,  H05K1/02 ,  H05K1/18 ,  H05K3/40 ,  G02B6/36

    CPC分类号： G02B6/4201 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48465 ,  H05K1/0219 ,  H05K1/189 ,  H05K3/403 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/10121 ,  H01L2924/00014 ,  H01L2924/00

    摘要： Concepts for conveniently arranging devices for the transduction of signals to and from voltage and current domains to infrared radiation domains is described. Specifically, optoelectronic components and methods of making the same are described. In one aspect, the optoelectronic component includes a base substrate having a pair of angled (or substantially perpendicular) faces with electrical traces extending therebetween. A semiconductor chip assembly is mounted on the first face of the base substrate and a photonic device is mounted on the second face. Both the semiconductor chip assembly and the photonic device are electrically connected to traces on the base substrate. The semiconductor chip assembly is generally arranged to be electrically connected to external devices. The photonic devices are generally arranged to optically communicate with one or more optical fibers. The described structure may be used with a wide variety of photonic devices. In some embodiments the base substrate is formed from a ceramic material having the electrical traces formed thereon. In other implementations the substrate includes a backing block having a flexible printed circuit substrate adhered thereto.

    摘要翻译： 描述了用于方便地布置用于将电压和电流域的信号传导到红外辐射域的装置的概念。 具体地说，描述了光电子元件及其制造方法。 在一个方面，光电子部件包括具有一对成角度（或基本上垂直）的表面的基底基板，其间延伸有电迹线。 半导体芯片组件安装在基底基板的第一面上，并且光子器件安装在第二面上。 半导体芯片组件和光子器件都与基底衬底上的迹线电连接。 半导体芯片组件通常被布置成电连接到外部装置。 光子器件通常布置成与一根或多根光纤光学通信。 所描述的结构可以与各种各样的光子器件一起使用。 在一些实施例中，基底由具有形成在其上的电迹线的陶瓷材料形成。 在其它实施方式中，基板包括具有粘附到其上的柔性印刷电路基板的背衬块。

    All-pass termination network with equalization and wide common-mode range
    7.
    发明授权
    All-pass termination network with equalization and wide common-mode range 有权
    全通终端网络具有均衡和宽共模范围

    公开(公告)号：US07649409B1

    公开(公告)日：2010-01-19

    申请号：US11877255

    申请日：2007-10-23

    申请人： Yongseon Koh ,  Babak Matinpour ,  Vijaya Ceekala ,  Ramsin Ziazadeh

    发明人： Yongseon Koh ,  Babak Matinpour ,  Vijaya Ceekala ,  Ramsin Ziazadeh

    IPC分类号： H03B1/00

    CPC分类号： H04B3/14 ,  H03F3/45085 ,  H03F3/45475

    摘要： An integrated circuit comprises a pin coupled to receive signals from outside the integrated circuit and an input network. The input network equalizes incoming signals by attenuating lower frequency input signals more than higher frequency input signals received at the pin. The input network is configured to generate a DC bias voltage at an output of the input network in response to an AC coupled input signal or a DC coupled input signal received at the pin with a wide common-mode range.

    摘要翻译： 集成电路包括被耦合以从集成电路外部接收信号的引脚和输入网络。 输入网络通过衰减低频输入信号来均衡输入信号，而不是在引脚处接收的高频输入信号。 输入网络被配置为响应于AC耦合输入信号或在具有宽共模范围的引脚处接收的DC耦合输入信号，在输入网络的输出处产生DC偏置电压。

    System and method for adaptively equalizing data signals with higher and lower data rates
    9.
    发明授权
    System and method for adaptively equalizing data signals with higher and lower data rates 有权
    用于以更高和更低数据速率自适应地均衡数据信号的系统和方法

    公开(公告)号：US08270463B1

    公开(公告)日：2012-09-18

    申请号：US13228249

    申请日：2011-09-08

    申请人： Amit Rane ,  Nicolas Nodenot ,  Yongseon Koh ,  Laurence Lewicki ,  Benjamin Buchanan

    发明人： Amit Rane ,  Nicolas Nodenot ,  Yongseon Koh ,  Laurence Lewicki ,  Benjamin Buchanan

    IPC分类号： H03H7/30

    CPC分类号： H04L25/03885 ,  H04B3/00 ,  H04L25/00

    摘要： System and method for adaptive signal equalizing in which overlapping data signal equalization paths provide cumulative data signal equalization to provide multiple equalized data signals having different available amounts of equalization. Signal slicing circuitry slices the equalized data signals to provide multiple sliced data signals, from which the sliced data signal selected as an output data signal is dependent upon the data rate of the incoming data signal.

    摘要翻译： 用于自适应信号均衡的系统和方法，其中重叠数据信号均衡路径提供累积数据信号均衡以提供具有不同可用量均衡的多个均衡数据信号。 信号分片电路对均衡的数据信号进行切片以提供多个分片数据信号，从中选择作为输出数据信号的分片数据信号取决于输入数据信号的数据速率。

    Semiconductor die with reduced RF attenuation
    10.
    发明授权
    Semiconductor die with reduced RF attenuation 有权
    半导体芯片具有降低的射频衰减

    公开(公告)号：US07598575B1

    公开(公告)日：2009-10-06

    申请号：US11900467

    申请日：2007-09-12

    申请人： Jeffrey A. Babcock ,  Yongseon Koh

    发明人： Jeffrey A. Babcock ,  Yongseon Koh

    IPC分类号： H01L27/088

    CPC分类号： H01L21/761 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The attenuation of an RF signal on a metal trace in a semiconductor die is substantially reduced by utilizing a number of RF blocking structures that lie on the surface of the substrate directly below the metal trace that carries the RF signal. The RF blocking structures include an isolation ring, and one or more doped regions that are formed inside the isolation ring.

    摘要翻译： 在半导体管芯中的金属迹线上的RF信号的衰减通过利用位于载体RF信号的金属迹线正下方的衬底的表面上的多个RF阻挡结构而大大降低。 RF阻挡结构包括隔离环和形成在隔离环内部的一个或多个掺杂区域。