公开(公告)号：US07777334B2

公开(公告)日：2010-08-17

申请号：US12070320

申请日：2008-02-15

申请人： Akinori Shindo ,  Masatoshi Tagaki ,  Hideaki Kurita

发明人： Akinori Shindo ,  Masatoshi Tagaki ,  Hideaki Kurita

IPC分类号： H01L23/485

CPC分类号： H01L24/13 ,  H01L21/823475 ,  H01L21/823481 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/13012 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/013

摘要： A semiconductor device comprising: a semiconductor layer including an element formation region, and first and second spaced apart isolation regions; an element in the element formation region; an interlayer dielectric layer above the semiconductor layer; an electrode pad above the interlayer dielectric layer; a passivation layer above the electrode pad and having an opening which exposes part of the electrode pad; and a bump in the opening and covering part of the element when viewed from a top side, the bump including a first edge when viewed from the top side, the first isolation region being formed in a first region, the first region including a first specific distance outward from a first line directly below the first edge of the bump, the second isolation region being formed in a second region, the second region including a second specific distance inward from the first line.

摘要翻译： 一种半导体器件，包括：半导体层，包括元件形成区域，以及第一和第二间隔开的隔离区域; 元素形成区域中的元素; 半导体层上方的层间电介质层; 层间介电层上方的电极焊盘; 在所述电极焊盘上方具有暴露所述电极焊盘的一部分的开口的钝化层; 以及当从顶侧观察时所述元件的开口和覆盖部分中的凸块，所述凸块包括从顶侧观察时的第一边缘，所述第一隔离区域形成在第一区域中，所述第一区域包括第一特定 从凸起的第一边缘正下方的第一线向外延伸，第二隔离区域形成在第二区域中，第二区域包括从第一线向内的第二特定距离。

公开(公告)号：US20080142967A1

公开(公告)日：2008-06-19

申请号：US12070321

申请日：2008-02-15

申请人： Akinori Shindo ,  Masatoshi Tagaki ,  Hideaki Kurita

发明人： Akinori Shindo ,  Masatoshi Tagaki ,  Hideaki Kurita

IPC分类号： H01L23/48

CPC分类号： H01L24/13 ,  H01L21/823475 ,  H01L21/823481 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/13012 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/013

摘要： A semiconductor device including: a semiconductor layer including an element formation region including an element; an interlayer dielectric layer above the semiconductor layer; an electrode pad above the interlayer dielectric layer; a passivation layer above the electrode pad and having an opening exposing at least part of the electrode pad; and a bump in the opening and covering at least part of the element, the bump including first and second edges, the semiconductor layer having a forbidden region including: a first specific distance outward from a first line directly below the first edge, a second specific distance inward from the first line, a third specific distance outward from a second line directly below the second edge, and a fourth specific distance inward from the second line.

摘要翻译： 一种半导体器件，包括：包括元件形成区域的半导体层，所述元件形成区域包括元件; 半导体层上方的层间电介质层; 层间介电层上方的电极焊盘; 在所述电极焊盘上方具有暴露至少部分所述电极焊盘的开口的钝化层; 并且在所述开口中的凸起并且覆盖所述元件的至少一部分，所述凸块包括第一和第二边缘，所述半导体层具有禁止区域，所述禁止区域包括：从所述第一边缘正下方的第一线向外的第一特定距离， 从第一线向内的距离，距离第二边缘正下方的第二线向外的第三特定距离以及从第二线向内的第四特定距离。

公开(公告)号：US20080142905A1

公开(公告)日：2008-06-19

申请号：US12070319

申请日：2008-02-15

申请人： Akinori Shindo ,  Masatoshi Tagaki ,  Hideaki Kurita

发明人： Akinori Shindo ,  Masatoshi Tagaki ,  Hideaki Kurita

IPC分类号： H01L27/088

CPC分类号： H01L24/13 ,  H01L21/823475 ,  H01L21/823481 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/13012 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/013

摘要： A semiconductor device including: a semiconductor layer including an element formation region including an element; a dielectric layer above the semiconductor; an electrode pad above the dielectric; a passivation layer above the pad and having an opening exposing part of the pad; and a bump in the opening and covering part of the element, the bump including first, second, third and fourth edges, the semiconductor having a forbidden region including: a first distance outward from a first line below the first edge, a second distance inward from the first line, a third distance outward from a second line below the second edge, a fourth distance inward from the second line, a fifth distance outward from a third line below the third edge, a sixth distance inward from the third line, a seventh distance outward from a fourth line below the fourth edge, and an eighth distance inward from the fourth line.

摘要翻译： 一种半导体器件，包括：包括元件形成区域的半导体层，所述元件形成区域包括元件; 半导体上方的电介质层; 电介质上方的电极垫; 在所述焊盘上方的钝化层，并且具有暴露所述焊盘部分的开口; 以及在所述元件的开口和覆盖部分中的凸块，所述凸块包括第一，第二，第三和第四边缘，所述半导体具有禁止区域，所述禁止区域包括：从所述第一边缘下方的第一线向外的第一距离，向内 从所述第一线向第二距离向外延伸，从所述第二边缘下方的第二线向外延伸，距离所述第二线向内的第四距离，距离所述第三边缘下方的第三线向外的第五距离，距所述第三条线的内侧的第六距离， 从第四边缘下方的第四线向外的第七距离，以及距离第四线向内的第八距离。

公开(公告)号：US20070007662A1

公开(公告)日：2007-01-11

申请号：US11478485

申请日：2006-06-29

申请人： Akinori Shindo ,  Masatoshi Tagaki ,  Hideaki Kurita

发明人： Akinori Shindo ,  Masatoshi Tagaki ,  Hideaki Kurita

IPC分类号： H01L23/48

CPC分类号： H01L24/13 ,  H01L21/823475 ,  H01L21/823481 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/13012 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/013

摘要： A semiconductor device including: a semiconductor layer including an element formation region and an isolation region provided around the element formation region; an element formed in the element formation region; an interlayer dielectric formed above the semiconductor layer; an electrode pad formed above the interlayer dielectric; a passivation layer formed above the electrode pad and having an opening which exposes at least part of the electrode pad; and a bump formed in the opening and having a rectangular planar shape having a short side and a long side, the bump at least partially covering the element when viewed from a top side, and the semiconductor layer positioned within a specific range inward and outward from a line extending vertically downward from the short side of the bump being a forbidden region.

摘要翻译： 一种半导体器件，包括：包括元件形成区域的半导体层和设置在元件形成区域周围的隔离区域; 元件形成区域中形成的元件; 形成在所述半导体层上方的层间电介质; 形成在层间电介质上方的电极焊盘; 钝化层，其形成在所述电极焊盘上方并且具有暴露所述电极焊盘的至少一部分的开口; 以及形成在所述开口中并且具有短边和长边的矩形平面形状的凸块，所述凸起从顶侧观察时至少部分地覆盖所述元件，并且所述半导体层位于从所述顶侧向内和向外的特定范围内 从凸起的短边垂直向下延伸的线是禁止区域。

公开(公告)号：US20060289961A1

公开(公告)日：2006-12-28

申请号：US11429581

申请日：2006-05-05

申请人： Akinori Shindo ,  Masatoshi Tagaki ,  Hideaki Kurita

发明人： Akinori Shindo ,  Masatoshi Tagaki ,  Hideaki Kurita

IPC分类号： H01L31/00

CPC分类号： H01L21/823462 ,  H01L27/088 ,  H01L29/1037 ,  H01L29/1041 ,  H01L29/42368 ,  H01L29/78 ,  H01L2224/05022 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/013

摘要： A semiconductor device including: a semiconductor layer; a transistor formed in the semiconductor layer and including a gate insulating layer and a gate electrode, the transistor being a high voltage transistor in which an insulating layer having a thickness greater than the thickness of the gate insulating layer is formed under an end portion of the gate electrode; an interlayer dielectric formed above the transistor; and an electrode pad formed above the interlayer dielectric and positioned over at least part of the gate electrode when viewed from a top side.

公开(公告)号：US07649260B2

公开(公告)日：2010-01-19

申请号：US11424891

申请日：2006-06-19

申请人： Akinori Shindo ,  Masatoshi Tagaki ,  Hideaki Kurita

发明人： Akinori Shindo ,  Masatoshi Tagaki ,  Hideaki Kurita

IPC分类号： H01L23/532

CPC分类号： H01L24/05 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device including: a semiconductor layer including an active region and an isolation region provided around the active region; an element formed in the active region; an interlayer dielectric formed above the semiconductor layer; and an electrode pad formed above the interlayer dielectric and having a rectangular planar shape having a short side and a long side, the electrode pad at least partially covering the element when viewed from a top side, and the semiconductor layer positioned in a specific range outward from a line extending vertically downward from the short side of the electrode pad being a forbidden region.

摘要翻译： 一种半导体器件，包括：半导体层，包括有源区和设置在有源区周围的隔离区; 在活性区域中形成的元素; 形成在所述半导体层上方的层间电介质; 以及形成在所述层间电介质的上方并具有短边和长边的矩形平面形状的电极焊盘，所述电极焊盘从顶侧观察时至少部分地覆盖所述元件，并且所述半导体层位于特定范围外侧 从作为禁止区域的电极焊盘的短边垂直向下延伸的线。

公开(公告)号：US07598569B2

公开(公告)日：2009-10-06

申请号：US11429581

申请日：2006-05-05

申请人： Akinori Shindo ,  Masatoshi Tagaki ,  Hideaki Kurita

发明人： Akinori Shindo ,  Masatoshi Tagaki ,  Hideaki Kurita

IPC分类号： H01L29/78

CPC分类号： H01L21/823462 ,  H01L27/088 ,  H01L29/1037 ,  H01L29/1041 ,  H01L29/42368 ,  H01L29/78 ,  H01L2224/05022 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/013

摘要： A semiconductor device including: a semiconductor layer; a transistor formed in the semiconductor layer and including a gate insulating layer and a gate electrode, the transistor being a high voltage transistor in which an insulating layer having a thickness greater than the thickness of the gate insulating layer is formed under an end portion of the gate electrode; an interlayer dielectric formed above the transistor; and an electrode pad formed above the interlayer dielectric and positioned over at least part of the gate electrode when viewed from a top side.

摘要翻译： 一种半导体器件，包括：半导体层; 形成在所述半导体层中并且包括栅极绝缘层和栅电极的晶体管，所述晶体管是高压晶体管，其中在所述栅极绝缘层的端部的下方形成有厚度大于所述栅极绝缘层的厚度的绝缘层 栅电极 形成在晶体管上方的层间电介质; 以及形成在所述层间电介质上方并且位于所述栅电极的至少一部分上方的电极焊盘，当从顶侧观察时。

公开(公告)号：US20080142906A1

公开(公告)日：2008-06-19

申请号：US12070320

申请日：2008-02-15

申请人： Akinori Shindo ,  Masatoshi Tagaki ,  Hideaki Kurita

发明人： Akinori Shindo ,  Masatoshi Tagaki ,  Hideaki Kurita

IPC分类号： H01L27/088

CPC分类号： H01L24/13 ,  H01L21/823475 ,  H01L21/823481 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/13012 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/013

摘要： A semiconductor device comprising: a semiconductor layer including an element formation region, and first and second spaced apart isolation regions; an element in the element formation region; an interlayer dielectric layer above the semiconductor layer; an electrode pad above the interlayer dielectric layer; a passivation layer above the electrode pad and having an opening which exposes part of the electrode pad; and a bump in the opening and covering part of the element when viewed from a top side, the bump including a first edge when viewed from the top side, the first isolation region being formed in a first region, the first region including a first specific distance outward from a first line directly below the first edge of the bump, the second isolation region being formed in a second region, the second region including a second specific distance inward from the first line.

摘要翻译： 一种半导体器件，包括：半导体层，包括元件形成区域，以及第一和第二间隔开的隔离区域; 元素形成区域中的元素; 半导体层上方的层间电介质层; 层间介电层上方的电极焊盘; 在所述电极焊盘上方具有暴露所述电极焊盘的一部分的开口的钝化层; 以及当从顶侧观察时所述元件的开口和覆盖部分中的凸块，所述凸块包括从顶侧观察时的第一边缘，所述第一隔离区域形成在第一区域中，所述第一区域包括第一特定 从凸起的第一边缘正下方的第一线向外延伸，第二隔离区域形成在第二区域中，第二区域包括从第一线向内的第二特定距离。

公开(公告)号：US08878365B2

公开(公告)日：2014-11-04

申请号：US13273613

申请日：2011-10-14

申请人： Takeshi Yuzawa ,  Masatoshi Tagaki

发明人： Takeshi Yuzawa ,  Masatoshi Tagaki

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L21/768 ,  H01L23/528 ,  H01L23/00

CPC分类号： H01L24/13 ,  H01L21/76838 ,  H01L23/528 ,  H01L24/11 ,  H01L2224/02165 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/13013 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/013

摘要： A semiconductor device, including: a semiconductor layer; a first conductive layer formed above the semiconductor layer and having a first width; a second conductive layer connected to the first conductive layer and having a second width which is smaller than the first width; an interlayer dielectric formed above the first conductive layer and the second conductive layer; and an electrode pad formed above the interlayer dielectric. A connection section at which the first conductive layer and the second conductive layer are connected is disposed in a specific region positioned inward from a line extending vertically downward from an edge of the electrode pad; and a reinforcing section is provided at the connection section.

摘要翻译： 一种半导体器件，包括：半导体层; 形成在所述半导体层上方并具有第一宽度的第一导电层; 连接到第一导电层并且具有小于第一宽度的第二宽度的第二导电层; 形成在所述第一导电层和所述第二导电层之上的层间电介质; 以及形成在层间电介质上方的电极焊盘。 连接第一导电层和第二导电层的连接部分设置在从电极焊盘的边缘垂直向下延伸的线的内侧的特定区域中; 并且在所述连接部设置有加强部。

公开(公告)号：US20070013065A1

公开(公告)日：2007-01-18

申请号：US11449796

申请日：2006-06-08

申请人： Takeshi Yuzawa ,  Masatoshi Tagaki

发明人： Takeshi Yuzawa ,  Masatoshi Tagaki

IPC分类号： H01L23/48

CPC分类号： H01L24/13 ,  H01L21/76838 ,  H01L23/528 ,  H01L24/11 ,  H01L2224/02165 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/13013 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/013

摘要： A semiconductor device, including: a semiconductor layer; a first conductive layer formed above the semiconductor layer and having a first width; a second conductive layer connected to the first conductive layer and having a second width which is smaller than the first width; an interlayer dielectric formed above the first conductive layer and the second conductive layer; and an electrode pad formed above the interlayer dielectric. A connection section at which the first conductive layer and the second conductive layer are connected is disposed in a specific region positioned inward from a line extending vertically downward from an edge of the electrode pad; and a reinforcing section is provided at the connection section.

摘要翻译： 一种半导体器件，包括：半导体层; 形成在所述半导体层上方并具有第一宽度的第一导电层; 连接到第一导电层并且具有小于第一宽度的第二宽度的第二导电层; 形成在所述第一导电层和所述第二导电层之上的层间电介质; 以及形成在层间电介质上方的电极焊盘。 连接第一导电层和第二导电层的连接部分设置在从电极焊盘的边缘垂直向下延伸的线的内侧的特定区域中; 并且在所述连接部设置有加强部。